* [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret.
@ 2025-01-16 2:40 ~yuming
2025-02-24 3:45 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: ~yuming @ 2025-01-16 2:40 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
From: Yu-Ming Chang <yumin686@andestech.com>
We only check RVC to allow 16-bit aligned return addreses. This will
cause issues when only ext_zca is enabled without RVC: 16-bit
instructions are allowed, but 16-bit aligned return address are not.
We should also check ext_zca to permit 16-bit aligned return addresses.
Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
---
The v2 has been updated to provide more explanation.
target/riscv/op_helper.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index eddedacf4b..891002f954 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -269,8 +269,10 @@ target_ulong helper_sret(CPURISCVState *env)
}
target_ulong retpc = env->sepc;
- if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
- riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
+ if ((retpc & 0x3) != 0) {
+ riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ }
}
if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
@@ -328,8 +330,10 @@ target_ulong helper_mret(CPURISCVState *env)
}
target_ulong retpc = env->mepc;
- if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
- riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
+ if ((retpc & 0x3) != 0) {
+ riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ }
}
uint64_t mstatus = env->mstatus;
--
2.45.3
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret.
2025-01-16 2:40 [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret ~yuming
@ 2025-02-24 3:45 ` Alistair Francis
2025-02-25 1:55 ` Yuming Yu-Ming Chang(張育銘)
0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2025-02-24 3:45 UTC (permalink / raw)
To: ~yuming
Cc: qemu-riscv, qemu-devel, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei
On Mon, Feb 3, 2025 at 3:34 PM ~yuming <yuming@git.sr.ht> wrote:
>
> From: Yu-Ming Chang <yumin686@andestech.com>
>
> We only check RVC to allow 16-bit aligned return addreses. This will
> cause issues when only ext_zca is enabled without RVC: 16-bit
> instructions are allowed, but 16-bit aligned return address are not.
> We should also check ext_zca to permit 16-bit aligned return addresses.
>
> Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
> ---
> The v2 has been updated to provide more explanation.
>
> target/riscv/op_helper.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index eddedacf4b..891002f954 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -269,8 +269,10 @@ target_ulong helper_sret(CPURISCVState *env)
> }
>
> target_ulong retpc = env->sepc;
> - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
You can just check ext_zca as C always implies Zca
Alistair
> + if ((retpc & 0x3) != 0) {
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + }
> }
>
> if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
> @@ -328,8 +330,10 @@ target_ulong helper_mret(CPURISCVState *env)
> }
>
> target_ulong retpc = env->mepc;
> - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
> + if ((retpc & 0x3) != 0) {
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + }
> }
>
> uint64_t mstatus = env->mstatus;
> --
> 2.45.3
>
^ permalink raw reply [flat|nested] 3+ messages in thread* RE: [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret.
2025-02-24 3:45 ` Alistair Francis
@ 2025-02-25 1:55 ` Yuming Yu-Ming Chang(張育銘)
0 siblings, 0 replies; 3+ messages in thread
From: Yuming Yu-Ming Chang(張育銘) @ 2025-02-25 1:55 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei
Hi Alistair,
I have sent another patch according to your suggestion:
[PATCH qemu] target/riscv: Only check ext_zca for 16-bit aligned PC.
Yuming
-----Original Message-----
From: Alistair Francis <alistair23@gmail.com>
Sent: Monday, February 24, 2025 11:45 AM
To: Yuming Yu-Ming Chang(張育銘) <yumin686@andestech.com>
Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; Palmer Dabbelt <palmer@dabbelt.com>; Alistair Francis <alistair.francis@wdc.com>; Bin Meng <bmeng.cn@gmail.com>; Weiwei Li <liwei1518@gmail.com>; Daniel Henrique Barboza <dbarboza@ventanamicro.com>; Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret.
[EXTERNAL MAIL]
On Mon, Feb 3, 2025 at 3:34 PM ~yuming <yuming@git.sr.ht> wrote:
>
> From: Yu-Ming Chang <yumin686@andestech.com>
>
> We only check RVC to allow 16-bit aligned return addreses. This will
> cause issues when only ext_zca is enabled without RVC: 16-bit
> instructions are allowed, but 16-bit aligned return address are not.
> We should also check ext_zca to permit 16-bit aligned return addresses.
>
> Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
> ---
> The v2 has been updated to provide more explanation.
>
> target/riscv/op_helper.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index eddedacf4b..891002f954 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -269,8 +269,10 @@ target_ulong helper_sret(CPURISCVState *env)
> }
>
> target_ulong retpc = env->sepc;
> - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
You can just check ext_zca as C always implies Zca
Alistair
> + if ((retpc & 0x3) != 0) {
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + }
> }
>
> if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
> @@ -328,8 +330,10 @@ target_ulong helper_mret(CPURISCVState *env)
> }
>
> target_ulong retpc = env->mepc;
> - if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
> + if ((retpc & 0x3) != 0) {
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + }
> }
>
> uint64_t mstatus = env->mstatus;
> --
> 2.45.3
>
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2025-01-16 2:40 [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret ~yuming
2025-02-24 3:45 ` Alistair Francis
2025-02-25 1:55 ` Yuming Yu-Ming Chang(張育銘)
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