[PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

[PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

[Guenter Roeck]

The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
The PHY on each may be connected to separate MDIO busses, or both may be
connected on the same MDIO bus using different PHY addresses. Add support
for it to the Cadence GEM emulation.

The Linux kernel checks the PCS disabled bit in the R_DESCONF register
to determine if SGMII is supported. If the bit is set, SGMII support is
disabled. Since the Microchip Icicle devicetree file configures SGMII
interface mode, enabling the Ethernet interfaces fails when booting
the Linux kernel. Add support for clearing the PCS disabled bit.

----------------------------------------------------------------
Guenter Roeck (4):
      hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
      hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
      hw/net/cadence_gem: Add pcs-enabled property
      microchip icicle: Enable PCS on Cadence Ethernet

 hw/net/cadence_gem.c         | 31 ++++++++++++++++++++++++-------
 hw/riscv/microchip_pfsoc.c   |  6 ++++++
 include/hw/net/cadence_gem.h |  4 ++++
 3 files changed, 34 insertions(+), 7 deletions(-)

[PATCH 1/4] hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus

[Guenter Roeck]

The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
The PHY on each may be connected to separate MDIO busses, or both may be
connected on the same MDIO bus using different PHY addresses.

To be able to support two PHY instances on a single MDIO bus, two properties
are needed: First, there needs to be a flag indicating if the MDIO bus on
a given Ethernet interface is connected. If not, attempts to read from this
bus must always return 0xffff. Implement this property as phy-connected.
Second, if the MDIO bus on an interface is active, it needs a link to the
consumer interface to be able to provide PHY access for it. Implement this
property as phy-consumer.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 hw/net/cadence_gem.c         | 24 ++++++++++++++++++------
 include/hw/net/cadence_gem.h |  3 +++
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 44446666de..520324adfd 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1541,12 +1541,20 @@ static void gem_handle_phy_access(CadenceGEMState *s)
 {
     uint32_t val = s->regs[R_PHYMNTNC];
     uint32_t phy_addr, reg_num;
+    CadenceGEMState *ps = s;
+    uint32_t op;
 
     phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
+    op = FIELD_EX32(val, PHYMNTNC, OP);
 
-    if (phy_addr != s->phy_addr) {
-        /* no phy at this address */
-        if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) {
+    /* Switch phy to consumer interface if there is an address match */
+    if (s->phy_consumer && phy_addr == s->phy_consumer->phy_addr) {
+        ps = s->phy_consumer;
+    }
+
+    if (!s->phy_connected || phy_addr != ps->phy_addr) {
+        /* phy not connected or no phy at this address */
+        if (op == MDIO_OP_READ) {
             s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff);
         }
         return;
@@ -1554,14 +1562,14 @@ static void gem_handle_phy_access(CadenceGEMState *s)
 
     reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
 
-    switch (FIELD_EX32(val, PHYMNTNC, OP)) {
+    switch (op) {
     case MDIO_OP_READ:
         s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA,
-                                         gem_phy_read(s, reg_num));
+                                         gem_phy_read(ps, reg_num));
         break;
 
     case MDIO_OP_WRITE:
-        gem_phy_write(s, reg_num, val);
+        gem_phy_write(ps, reg_num, val);
         break;
 
     default:
@@ -1813,6 +1821,10 @@ static const Property gem_properties[] = {
                       num_type2_screeners, 4),
     DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
                        jumbo_max_len, 10240),
+    DEFINE_PROP_BOOL("phy-connected", CadenceGEMState, phy_connected, true),
+    DEFINE_PROP_LINK("phy-consumer", CadenceGEMState, phy_consumer,
+                     TYPE_CADENCE_GEM, CadenceGEMState *),
+
     DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr,
                      TYPE_MEMORY_REGION, MemoryRegion *),
 };
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 91ebb5c8ae..21e7319f53 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -81,6 +81,9 @@ struct CadenceGEMState {
 
     uint8_t phy_loop; /* Are we in phy loopback? */
 
+    bool phy_connected; /* true if connected */
+    struct CadenceGEMState *phy_consumer;
+
     /* The current DMA descriptor pointers */
     uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
     uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
-- 
2.45.2

[PATCH 2/4] hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels

[Guenter Roeck]

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 hw/riscv/microchip_pfsoc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index ba1d090d9b..6e2a6e721b 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -414,6 +414,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
 
     object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
     object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
+    object_property_set_bool(OBJECT(&s->gem0), "phy-connected", false, errp);
+
     sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
                     memmap[MICROCHIP_PFSOC_GEM0].base);
@@ -422,6 +424,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
 
     object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
     object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
+    object_property_set_link(OBJECT(&s->gem1), "phy-consumer",
+                             OBJECT(&s->gem0), errp);
     sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
                     memmap[MICROCHIP_PFSOC_GEM1].base);
-- 
2.45.2

[PATCH 3/4] hw/net/cadence_gem: Add pcs-enabled property

[Guenter Roeck]

The Linux kernel checks the PCS disabled bit in the R_DESCONF register
to determine if SGMII is supported. If the bit is set, SGMII support is
disabled. Since the Microchip Icicle devicetree file configures SGMII
interface mode, enabling the Ethernet interfaces fails when booting
the Linux kernel.

Add pcs-enabled property to to let the driver know if PCS should be
enabled. Set the flag to false by default (indicating that PCS is disabled)
to match the exiting code.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 hw/net/cadence_gem.c         | 7 ++++++-
 include/hw/net/cadence_gem.h | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 520324adfd..44896f1801 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1477,7 +1477,10 @@ static void gem_reset(DeviceState *d)
     s->regs[R_TXPARTIALSF] = 0x000003ff;
     s->regs[R_RXPARTIALSF] = 0x000003ff;
     s->regs[R_MODID] = s->revision;
-    s->regs[R_DESCONF] = 0x02D00111;
+    s->regs[R_DESCONF] = 0x02D00110;
+    if (!s->pcs_enabled) {
+        s->regs[R_DESCONF] |= 0x00000001;
+    }
     s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
     s->regs[R_DESCONF5] = 0x002f2045;
     s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
@@ -1821,6 +1824,8 @@ static const Property gem_properties[] = {
                       num_type2_screeners, 4),
     DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
                        jumbo_max_len, 10240),
+    DEFINE_PROP_BOOL("pcs-enabled", CadenceGEMState,
+                       pcs_enabled, false),
     DEFINE_PROP_BOOL("phy-connected", CadenceGEMState, phy_connected, true),
     DEFINE_PROP_LINK("phy-consumer", CadenceGEMState, phy_consumer,
                      TYPE_CADENCE_GEM, CadenceGEMState *),
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 21e7319f53..e63941f18f 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -62,6 +62,7 @@ struct CadenceGEMState {
     uint8_t num_type2_screeners;
     uint32_t revision;
     uint16_t jumbo_max_len;
+    bool pcs_enabled;
 
     /* GEM registers backing store */
     uint32_t regs[CADENCE_GEM_MAXREG];
-- 
2.45.2

[PATCH 4/4] microchip icicle: Enable PCS on Cadence Ethernet

[Guenter Roeck]

PCS needs to be enabled for SGMII to be supported by the Linux kernel.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
---
 hw/riscv/microchip_pfsoc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 6e2a6e721b..5d3007e8d3 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -415,6 +415,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
     object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
     object_property_set_bool(OBJECT(&s->gem0), "phy-connected", false, errp);
+    object_property_set_bool(OBJECT(&s->gem0), "pcs-enabled", true, errp);
 
     sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
@@ -426,6 +427,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
     object_property_set_link(OBJECT(&s->gem1), "phy-consumer",
                              OBJECT(&s->gem0), errp);
+    object_property_set_bool(OBJECT(&s->gem1), "pcs-enabled", true, errp);
     sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
                     memmap[MICROCHIP_PFSOC_GEM1].base);
-- 
2.45.2

Re: [PATCH 1/4] hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus

[Alistair Francis]

On Sun, Oct 5, 2025 at 6:03 AM Guenter Roeck <linux@roeck-us.net> wrote:
>
> The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
> The PHY on each may be connected to separate MDIO busses, or both may be
> connected on the same MDIO bus using different PHY addresses.
>
> To be able to support two PHY instances on a single MDIO bus, two properties
> are needed: First, there needs to be a flag indicating if the MDIO bus on
> a given Ethernet interface is connected. If not, attempts to read from this
> bus must always return 0xffff. Implement this property as phy-connected.
> Second, if the MDIO bus on an interface is active, it needs a link to the
> consumer interface to be able to provide PHY access for it. Implement this
> property as phy-consumer.
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/net/cadence_gem.c         | 24 ++++++++++++++++++------
>  include/hw/net/cadence_gem.h |  3 +++
>  2 files changed, 21 insertions(+), 6 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 44446666de..520324adfd 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1541,12 +1541,20 @@ static void gem_handle_phy_access(CadenceGEMState *s)
>  {
>      uint32_t val = s->regs[R_PHYMNTNC];
>      uint32_t phy_addr, reg_num;
> +    CadenceGEMState *ps = s;
> +    uint32_t op;
>
>      phy_addr = FIELD_EX32(val, PHYMNTNC, PHY_ADDR);
> +    op = FIELD_EX32(val, PHYMNTNC, OP);
>
> -    if (phy_addr != s->phy_addr) {
> -        /* no phy at this address */
> -        if (FIELD_EX32(val, PHYMNTNC, OP) == MDIO_OP_READ) {
> +    /* Switch phy to consumer interface if there is an address match */
> +    if (s->phy_consumer && phy_addr == s->phy_consumer->phy_addr) {
> +        ps = s->phy_consumer;
> +    }
> +
> +    if (!s->phy_connected || phy_addr != ps->phy_addr) {
> +        /* phy not connected or no phy at this address */
> +        if (op == MDIO_OP_READ) {
>              s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA, 0xffff);
>          }
>          return;
> @@ -1554,14 +1562,14 @@ static void gem_handle_phy_access(CadenceGEMState *s)
>
>      reg_num = FIELD_EX32(val, PHYMNTNC, REG_ADDR);
>
> -    switch (FIELD_EX32(val, PHYMNTNC, OP)) {
> +    switch (op) {
>      case MDIO_OP_READ:
>          s->regs[R_PHYMNTNC] = FIELD_DP32(val, PHYMNTNC, DATA,
> -                                         gem_phy_read(s, reg_num));
> +                                         gem_phy_read(ps, reg_num));
>          break;
>
>      case MDIO_OP_WRITE:
> -        gem_phy_write(s, reg_num, val);
> +        gem_phy_write(ps, reg_num, val);
>          break;
>
>      default:
> @@ -1813,6 +1821,10 @@ static const Property gem_properties[] = {
>                        num_type2_screeners, 4),
>      DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
>                         jumbo_max_len, 10240),
> +    DEFINE_PROP_BOOL("phy-connected", CadenceGEMState, phy_connected, true),
> +    DEFINE_PROP_LINK("phy-consumer", CadenceGEMState, phy_consumer,
> +                     TYPE_CADENCE_GEM, CadenceGEMState *),
> +
>      DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr,
>                       TYPE_MEMORY_REGION, MemoryRegion *),
>  };
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index 91ebb5c8ae..21e7319f53 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -81,6 +81,9 @@ struct CadenceGEMState {
>
>      uint8_t phy_loop; /* Are we in phy loopback? */
>
> +    bool phy_connected; /* true if connected */
> +    struct CadenceGEMState *phy_consumer;
> +
>      /* The current DMA descriptor pointers */
>      uint32_t rx_desc_addr[MAX_PRIORITY_QUEUES];
>      uint32_t tx_desc_addr[MAX_PRIORITY_QUEUES];
> --
> 2.45.2
>
>

Re: [PATCH 2/4] hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels

[Alistair Francis]

On Sun, Oct 5, 2025 at 6:03 AM Guenter Roeck <linux@roeck-us.net> wrote:
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/microchip_pfsoc.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index ba1d090d9b..6e2a6e721b 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -414,6 +414,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>
>      object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
>      object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
> +    object_property_set_bool(OBJECT(&s->gem0), "phy-connected", false, errp);
> +
>      sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
>                      memmap[MICROCHIP_PFSOC_GEM0].base);
> @@ -422,6 +424,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>
>      object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
>      object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
> +    object_property_set_link(OBJECT(&s->gem1), "phy-consumer",
> +                             OBJECT(&s->gem0), errp);
>      sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
>                      memmap[MICROCHIP_PFSOC_GEM1].base);
> --
> 2.45.2
>
>

Re: [PATCH 3/4] hw/net/cadence_gem: Add pcs-enabled property

[Alistair Francis]

On Sun, Oct 5, 2025 at 6:03 AM Guenter Roeck <linux@roeck-us.net> wrote:
>
> The Linux kernel checks the PCS disabled bit in the R_DESCONF register
> to determine if SGMII is supported. If the bit is set, SGMII support is
> disabled. Since the Microchip Icicle devicetree file configures SGMII
> interface mode, enabling the Ethernet interfaces fails when booting
> the Linux kernel.
>
> Add pcs-enabled property to to let the driver know if PCS should be
> enabled. Set the flag to false by default (indicating that PCS is disabled)
> to match the exiting code.
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/net/cadence_gem.c         | 7 ++++++-
>  include/hw/net/cadence_gem.h | 1 +
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 520324adfd..44896f1801 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -1477,7 +1477,10 @@ static void gem_reset(DeviceState *d)
>      s->regs[R_TXPARTIALSF] = 0x000003ff;
>      s->regs[R_RXPARTIALSF] = 0x000003ff;
>      s->regs[R_MODID] = s->revision;
> -    s->regs[R_DESCONF] = 0x02D00111;
> +    s->regs[R_DESCONF] = 0x02D00110;
> +    if (!s->pcs_enabled) {
> +        s->regs[R_DESCONF] |= 0x00000001;
> +    }
>      s->regs[R_DESCONF2] = 0x2ab10000 | s->jumbo_max_len;
>      s->regs[R_DESCONF5] = 0x002f2045;
>      s->regs[R_DESCONF6] = R_DESCONF6_DMA_ADDR_64B_MASK;
> @@ -1821,6 +1824,8 @@ static const Property gem_properties[] = {
>                        num_type2_screeners, 4),
>      DEFINE_PROP_UINT16("jumbo-max-len", CadenceGEMState,
>                         jumbo_max_len, 10240),
> +    DEFINE_PROP_BOOL("pcs-enabled", CadenceGEMState,
> +                       pcs_enabled, false),
>      DEFINE_PROP_BOOL("phy-connected", CadenceGEMState, phy_connected, true),
>      DEFINE_PROP_LINK("phy-consumer", CadenceGEMState, phy_consumer,
>                       TYPE_CADENCE_GEM, CadenceGEMState *),
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index 21e7319f53..e63941f18f 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -62,6 +62,7 @@ struct CadenceGEMState {
>      uint8_t num_type2_screeners;
>      uint32_t revision;
>      uint16_t jumbo_max_len;
> +    bool pcs_enabled;
>
>      /* GEM registers backing store */
>      uint32_t regs[CADENCE_GEM_MAXREG];
> --
> 2.45.2
>
>

Re: [PATCH 4/4] microchip icicle: Enable PCS on Cadence Ethernet

[Alistair Francis]

On Sun, Oct 5, 2025 at 6:03 AM Guenter Roeck <linux@roeck-us.net> wrote:
>
> PCS needs to be enabled for SGMII to be supported by the Linux kernel.
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/microchip_pfsoc.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 6e2a6e721b..5d3007e8d3 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -415,6 +415,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>      object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
>      object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
>      object_property_set_bool(OBJECT(&s->gem0), "phy-connected", false, errp);
> +    object_property_set_bool(OBJECT(&s->gem0), "pcs-enabled", true, errp);
>
>      sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
> @@ -426,6 +427,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
>      object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
>      object_property_set_link(OBJECT(&s->gem1), "phy-consumer",
>                               OBJECT(&s->gem0), errp);
> +    object_property_set_bool(OBJECT(&s->gem1), "pcs-enabled", true, errp);
>      sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
>      sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
>                      memmap[MICROCHIP_PFSOC_GEM1].base);
> --
> 2.45.2
>
>

Re: [PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

[Alistair Francis]

On Sun, Oct 5, 2025 at 6:02 AM Guenter Roeck <linux@roeck-us.net> wrote:
>
> The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
> The PHY on each may be connected to separate MDIO busses, or both may be
> connected on the same MDIO bus using different PHY addresses. Add support
> for it to the Cadence GEM emulation.
>
> The Linux kernel checks the PCS disabled bit in the R_DESCONF register
> to determine if SGMII is supported. If the bit is set, SGMII support is
> disabled. Since the Microchip Icicle devicetree file configures SGMII
> interface mode, enabling the Ethernet interfaces fails when booting
> the Linux kernel. Add support for clearing the PCS disabled bit.
>
> ----------------------------------------------------------------
> Guenter Roeck (4):
>       hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
>       hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
>       hw/net/cadence_gem: Add pcs-enabled property
>       microchip icicle: Enable PCS on Cadence Ethernet

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  hw/net/cadence_gem.c         | 31 ++++++++++++++++++++++++-------
>  hw/riscv/microchip_pfsoc.c   |  6 ++++++
>  include/hw/net/cadence_gem.h |  4 ++++
>  3 files changed, 34 insertions(+), 7 deletions(-)
>

Re: [PATCH 0/4] Fix Ethernet interface support for microchip-icicle-kit

[Conor Dooley]

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On Wed, Oct 15, 2025 at 01:03:50PM +1000, Alistair Francis wrote:
> On Sun, Oct 5, 2025 at 6:02 AM Guenter Roeck <linux@roeck-us.net> wrote:
> >
> > The Microchip PolarFire SoC Icicle Kit supports two Ethernet interfaces.
> > The PHY on each may be connected to separate MDIO busses, or both may be
> > connected on the same MDIO bus using different PHY addresses. Add support
> > for it to the Cadence GEM emulation.
> >
> > The Linux kernel checks the PCS disabled bit in the R_DESCONF register
> > to determine if SGMII is supported. If the bit is set, SGMII support is
> > disabled. Since the Microchip Icicle devicetree file configures SGMII
> > interface mode, enabling the Ethernet interfaces fails when booting
> > the Linux kernel. Add support for clearing the PCS disabled bit.
> >
> > ----------------------------------------------------------------
> > Guenter Roeck (4):
> >       hw/net/cadence_gem: Support two Ethernet interfaces connected to single MDIO bus
> >       hw/riscv: microchip_pfsoc: Connect Ethernet PHY channels
> >       hw/net/cadence_gem: Add pcs-enabled property
> >       microchip icicle: Enable PCS on Cadence Ethernet
> 
> Thanks!
> 
> Applied to riscv-to-apply.next

Didn't notice these in time, thanks for fixing this Guenter.

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