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From: Alistair Francis <alistair23@gmail.com>
To: liweiwei <liweiwei@iscas.ac.cn>
Cc: lazyparser@gmail.com, "open list:RISC-V" <qemu-riscv@nongnu.org>,
	lustrew@foxmail.com, wangjunqiang <wangjunqiang@iscas.ac.cn>,
	Bin Meng <bin.meng@windriver.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	luruibo2000@163.com, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties
Date: Mon, 10 Jan 2022 17:06:37 +1000	[thread overview]
Message-ID: <CAKmqyKOQ081MRKveGu6LyAdcZYsPbv5NwWUiu8wptfkFuNCsLw@mail.gmail.com> (raw)
In-Reply-To: <20211230143058.7352-8-liweiwei@iscas.ac.cn>

On Fri, Dec 31, 2021 at 12:32 AM liweiwei <liweiwei@iscas.ac.cn> wrote:
>
> Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
> Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
> ---
>  target/riscv/cpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 961c5f4334..6575ec8cfa 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -668,6 +668,19 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>      DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>      DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> +    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
> +    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
> +    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
> +    DEFINE_PROP_BOOL("x-zk", RISCVCPU, cfg.ext_zk, false),
> +    DEFINE_PROP_BOOL("x-zkn", RISCVCPU, cfg.ext_zkn, false),
> +    DEFINE_PROP_BOOL("x-zknd", RISCVCPU, cfg.ext_zknd, false),
> +    DEFINE_PROP_BOOL("x-zkne", RISCVCPU, cfg.ext_zkne, false),
> +    DEFINE_PROP_BOOL("x-zknh", RISCVCPU, cfg.ext_zknh, false),
> +    DEFINE_PROP_BOOL("x-zkr", RISCVCPU, cfg.ext_zkr, false),
> +    DEFINE_PROP_BOOL("x-zks", RISCVCPU, cfg.ext_zks, false),
> +    DEFINE_PROP_BOOL("x-zksed", RISCVCPU, cfg.ext_zksed, false),
> +    DEFINE_PROP_BOOL("x-zksh", RISCVCPU, cfg.ext_zksh, false),
> +    DEFINE_PROP_BOOL("x-zkt", RISCVCPU, cfg.ext_zkt, false),

These are ratified specs, so these don't need to be marked as
experimental, you can drop the "x-".

Alistair

>      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
>      DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
>      /* ePMP 0.9.3 */
> --
> 2.17.1
>
>


  reply	other threads:[~2022-01-10  7:11 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-30 14:30 [PATCH v3 0/7] support subsets of scalar crypto extension liweiwei
2021-12-30 14:30 ` [PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk* liweiwei
2021-12-31  2:04   ` Bin Meng
2021-12-31  2:29     ` liweiwei
2021-12-30 14:30 ` [PATCH v3 2/7] target/riscv: rvk: add implementation of instructions for Zbk* liweiwei
2021-12-30 14:30 ` [PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto liweiwei
2021-12-30 14:46   ` Philippe Mathieu-Daudé
2021-12-30 15:24     ` liweiwei
2021-12-30 14:30 ` [PATCH v3 4/7] target/riscv: rvk: add implementation of instructions for Zk* liweiwei
2021-12-30 14:30 ` [PATCH v3 5/7] target/riscv: rvk: add CSR support for Zkr liweiwei
2021-12-30 14:30 ` [PATCH v3 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions liweiwei
2021-12-30 14:30 ` [PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties liweiwei
2022-01-10  7:06   ` Alistair Francis [this message]
2022-01-10  7:44     ` Weiwei Li

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