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X-Received-From: 2a00:1450:4864:20::143 Subject: Re: [Qemu-devel] [PATCH v5 21/30] riscv: sifive_u: Add PRCI block to the SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Palmer Dabbelt , Alistair Francis , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Aug 22, 2019 at 10:35 PM Bin Meng wrote: > > Add PRCI mmio base address and size mappings to sifive_u machine, > and generate the corresponding device tree node. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > > --- > > Changes in v5: > - create sifive_u_prci block directly in the machine codes, instead > of calling sifive_u_prci_create() > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > hw/riscv/sifive_u.c | 24 +++++++++++++++++++++++- > include/hw/riscv/sifive_u.h | 3 +++ > 2 files changed, 26 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 08db741..c777d41 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -9,6 +9,7 @@ > * 0) UART > * 1) CLINT (Core Level Interruptor) > * 2) PLIC (Platform Level Interrupt Controller) > + * 3) PRCI (Power, Reset, Clock, Interrupt) > * > * This board currently generates devicetree dynamically that indicates at least > * two harts and up to five harts. > @@ -61,6 +62,7 @@ static const struct MemmapEntry { > [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, > [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, > [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, > + [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, > [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, > [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, > [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, > @@ -78,7 +80,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > uint32_t *cells; > char *nodename; > char ethclk_names[] = "pclk\0hclk\0tx_clk"; > - uint32_t plic_phandle, ethclk_phandle, phandle = 1; > + uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1; > uint32_t uartclk_phandle; > uint32_t hfclk_phandle, rtcclk_phandle; > > @@ -189,6 +191,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > g_free(cells); > g_free(nodename); > > + prci_phandle = phandle++; > + nodename = g_strdup_printf("/soc/clock-controller@%lx", > + (long)memmap[SIFIVE_U_PRCI].base); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); > + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); > + qemu_fdt_setprop_cells(fdt, nodename, "clocks", > + hfclk_phandle, rtcclk_phandle); > + qemu_fdt_setprop_cells(fdt, nodename, "reg", > + 0x0, memmap[SIFIVE_U_PRCI].base, > + 0x0, memmap[SIFIVE_U_PRCI].size); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", > + "sifive,fu540-c000-prci"); > + g_free(nodename); > + > plic_phandle = phandle++; > cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); > for (cpu = 0; cpu < ms->smp.cpus; cpu++) { > @@ -411,6 +428,8 @@ static void riscv_sifive_u_soc_init(Object *obj) > "cpu-type", &error_abort); > } > > + sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), > + TYPE_SIFIVE_U_PRCI); > sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), > TYPE_CADENCE_GEM); > } > @@ -484,6 +503,9 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) > memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); > > + object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); > + > for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { > plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); > } > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index debbf28..2a023be 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -21,6 +21,7 @@ > > #include "hw/net/cadence_gem.h" > #include "hw/riscv/sifive_cpu.h" > +#include "hw/riscv/sifive_u_prci.h" > > #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" > #define RISCV_U_SOC(obj) \ > @@ -36,6 +37,7 @@ typedef struct SiFiveUSoCState { > RISCVHartArrayState e_cpus; > RISCVHartArrayState u_cpus; > DeviceState *plic; > + SiFiveUPRCIState prci; > CadenceGEMState gem; > } SiFiveUSoCState; > > @@ -54,6 +56,7 @@ enum { > SIFIVE_U_MROM, > SIFIVE_U_CLINT, > SIFIVE_U_PLIC, > + SIFIVE_U_PRCI, > SIFIVE_U_UART0, > SIFIVE_U_UART1, > SIFIVE_U_DRAM, > -- > 2.7.4 > >