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Wed, 23 Apr 2025 17:37:46 -0700 (PDT) MIME-Version: 1.0 References: <20250406070254.274797-1-pbonzini@redhat.com> <20250406070254.274797-24-pbonzini@redhat.com> In-Reply-To: <20250406070254.274797-24-pbonzini@redhat.com> From: Alistair Francis Date: Thu, 24 Apr 2025 10:37:21 +1000 X-Gm-Features: ATxdqUHa95z4NHnAN8xsbxzJs-Rtoh-7gpaZDXz-xVDDM1fFQlDnmf1beM4f5Gc Message-ID: Subject: Re: [PATCH 23/27] target/riscv: convert TT C906 to RISCVCPUDef To: Paolo Bonzini Cc: qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Apr 6, 2025 at 5:03=E2=80=AFPM Paolo Bonzini = wrote: > > Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 61 +++++++++++++++++++++------------------------- > 1 file changed, 28 insertions(+), 33 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9669e9822b2..45bed28ea8a 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -500,38 +500,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu= , const RISCVCSR *csr_list) > #endif > > #if defined(TARGET_RISCV64) > -static void rv64_thead_c906_cpu_init(Object *obj) > -{ > - CPURISCVState *env =3D &RISCV_CPU(obj)->env; > - RISCVCPU *cpu =3D RISCV_CPU(obj); > - > - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); > - env->priv_ver =3D PRIV_VERSION_1_11_0; > - > - cpu->cfg.ext_zfa =3D true; > - cpu->cfg.ext_zfh =3D true; > - cpu->cfg.mmu =3D true; > - cpu->cfg.ext_xtheadba =3D true; > - cpu->cfg.ext_xtheadbb =3D true; > - cpu->cfg.ext_xtheadbs =3D true; > - cpu->cfg.ext_xtheadcmo =3D true; > - cpu->cfg.ext_xtheadcondmov =3D true; > - cpu->cfg.ext_xtheadfmemidx =3D true; > - cpu->cfg.ext_xtheadmac =3D true; > - cpu->cfg.ext_xtheadmemidx =3D true; > - cpu->cfg.ext_xtheadmempair =3D true; > - cpu->cfg.ext_xtheadsync =3D true; > - > - cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; > -#ifndef CONFIG_USER_ONLY > - set_satp_mode_max_supported(cpu, VM_1_10_SV39); > - riscv_register_custom_csrs(cpu, th_csr_list); > -#endif > - > - /* inherited from parent obj via riscv_cpu_init() */ > - cpu->cfg.pmp =3D true; > -} > - > static void rv64_veyron_v1_cpu_init(Object *obj) > { > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > @@ -3221,7 +3189,34 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { > .misa_mxl_max =3D MXL_RV64, > ), > > - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c= 906_cpu_init), > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_THEAD_C906, TYPE_RISCV_VENDOR_CPU, > + .misa_mxl_max =3D MXL_RV64, > + .misa_ext =3D RVG | RVC | RVS | RVU, > + .priv_spec =3D PRIV_VERSION_1_11_0, > + > + .cfg.ext_zfa =3D true, > + .cfg.ext_zfh =3D true, > + .cfg.mmu =3D true, > + .cfg.ext_xtheadba =3D true, > + .cfg.ext_xtheadbb =3D true, > + .cfg.ext_xtheadbs =3D true, > + .cfg.ext_xtheadcmo =3D true, > + .cfg.ext_xtheadcondmov =3D true, > + .cfg.ext_xtheadfmemidx =3D true, > + .cfg.ext_xtheadmac =3D true, > + .cfg.ext_xtheadmemidx =3D true, > + .cfg.ext_xtheadmempair =3D true, > + .cfg.ext_xtheadsync =3D true, > + .cfg.pmp =3D true, > + > + .cfg.mvendorid =3D THEAD_VENDOR_ID, > + > + .cfg.max_satp_mode =3D VM_1_10_SV39, > +#ifndef CONFIG_USER_ONLY > + .custom_csrs =3D th_csr_list, > +#endif > + ), > + > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_asca= lon_cpu_init), > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_= v1_cpu_init), > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, > -- > 2.49.0 >