Re: [PATCH 2/2] hw/intc: Don't clear pending bits on IRQ lowering

[Alistair Francis <alistair23@gmail.com>]

On Thu, Sep 19, 2024 at 12:03 AM Sergey Makarov <s.makarov@syntacore.com> wrote:
>
> According to PLIC specification (chapter 5), there
> is only one case, when interrupt is claimed. Fix
> PLIC controller to match this behavior.
>
> Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/intc/sifive_plic.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 3f3ee96ebc..deec162630 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -354,8 +354,10 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
>  {
>      SiFivePLICState *s = opaque;
>
> -    sifive_plic_set_pending(s, irq, level > 0);
> -    sifive_plic_update(s);
> +    if (level > 0) {
> +        sifive_plic_set_pending(s, irq, true);
> +        sifive_plic_update(s);
> +    }
>  }
>
>  static void sifive_plic_realize(DeviceState *dev, Error **errp)
> --
> 2.34.1
>
>