* [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
@ 2019-04-01 19:12 Jonathan Behrens
2019-04-02 0:25 ` Richard Henderson
2019-04-03 23:10 ` Alistair Francis
0 siblings, 2 replies; 9+ messages in thread
From: Jonathan Behrens @ 2019-04-01 19:12 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, qemu-riscv
The 'sfence.vma' instruction is privileged, and should only ever be allowed
when executing in supervisor mode or higher.
Jonathan
Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
---
target/riscv/op_helper.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index b7dc18a41e..644d0fb35f 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- if (env->priv == PRV_S &&
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TVM)) {
+ if (!(env->priv >= PRV_S) ||
+ (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
--
2.20.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-01 19:12 [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode Jonathan Behrens
@ 2019-04-02 0:25 ` Richard Henderson
2019-04-03 23:10 ` Alistair Francis
1 sibling, 0 replies; 9+ messages in thread
From: Richard Henderson @ 2019-04-02 0:25 UTC (permalink / raw)
To: Jonathan Behrens, qemu-devel
Cc: Bastian Koppelmann, Palmer Dabbelt, Alistair Francis, qemu-riscv,
Sagar Karandikar
On 4/2/19 2:12 AM, Jonathan Behrens wrote:
> The 'sfence.vma' instruction is privileged, and should only ever be allowed
> when executing in supervisor mode or higher.
>
> Jonathan
>
> Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
> ---
> target/riscv/op_helper.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-01 19:12 [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode Jonathan Behrens
2019-04-02 0:25 ` Richard Henderson
@ 2019-04-03 23:10 ` Alistair Francis
2019-04-12 21:14 ` Jonathan Behrens
1 sibling, 1 reply; 9+ messages in thread
From: Alistair Francis @ 2019-04-03 23:10 UTC (permalink / raw)
To: Jonathan Behrens
Cc: qemu-devel@nongnu.org Developers, Bastian Koppelmann,
Palmer Dabbelt, Alistair Francis, open list:RISC-V,
Sagar Karandikar
On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>
> The 'sfence.vma' instruction is privileged, and should only ever be allowed
> when executing in supervisor mode or higher.
>
> Jonathan
>
> Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/op_helper.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index b7dc18a41e..644d0fb35f 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
> {
> RISCVCPU *cpu = riscv_env_get_cpu(env);
> CPUState *cs = CPU(cpu);
> - if (env->priv == PRV_S &&
> - env->priv_ver >= PRIV_VERSION_1_10_0 &&
> - get_field(env->mstatus, MSTATUS_TVM)) {
> + if (!(env->priv >= PRV_S) ||
> + (env->priv == PRV_S &&
> + env->priv_ver >= PRIV_VERSION_1_10_0 &&
> + get_field(env->mstatus, MSTATUS_TVM))) {
> riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> } else {
> tlb_flush(cs);
> --
> 2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-03 23:10 ` Alistair Francis
@ 2019-04-12 21:14 ` Jonathan Behrens
2019-04-12 21:14 ` Jonathan Behrens
2019-04-12 21:23 ` Alistair Francis
0 siblings, 2 replies; 9+ messages in thread
From: Jonathan Behrens @ 2019-04-12 21:14 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, Bastian Koppelmann,
Palmer Dabbelt, Alistair Francis, open list:RISC-V,
Sagar Karandikar
Just to double check, nothing further on this is need from me, right? It is
set to be merged onto the master branch once the 4.0 release is out?
Jonathan
On Wed, Apr 3, 2019 at 7:11 PM Alistair Francis <alistair23@gmail.com>
wrote:
> On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <fintelia@gmail.com>
> wrote:
> >
> > The 'sfence.vma' instruction is privileged, and should only ever be
> allowed
> > when executing in supervisor mode or higher.
> >
> > Jonathan
> >
> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
>
> > ---
> > target/riscv/op_helper.c | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> > index b7dc18a41e..644d0fb35f 100644
> > --- a/target/riscv/op_helper.c
> > +++ b/target/riscv/op_helper.c
> > @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
> > {
> > RISCVCPU *cpu = riscv_env_get_cpu(env);
> > CPUState *cs = CPU(cpu);
> > - if (env->priv == PRV_S &&
> > - env->priv_ver >= PRIV_VERSION_1_10_0 &&
> > - get_field(env->mstatus, MSTATUS_TVM)) {
> > + if (!(env->priv >= PRV_S) ||
> > + (env->priv == PRV_S &&
> > + env->priv_ver >= PRIV_VERSION_1_10_0 &&
> > + get_field(env->mstatus, MSTATUS_TVM))) {
> > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> > } else {
> > tlb_flush(cs);
> > --
> > 2.20.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-12 21:14 ` Jonathan Behrens
@ 2019-04-12 21:14 ` Jonathan Behrens
2019-04-12 21:23 ` Alistair Francis
1 sibling, 0 replies; 9+ messages in thread
From: Jonathan Behrens @ 2019-04-12 21:14 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
Just to double check, nothing further on this is need from me, right? It is
set to be merged onto the master branch once the 4.0 release is out?
Jonathan
On Wed, Apr 3, 2019 at 7:11 PM Alistair Francis <alistair23@gmail.com>
wrote:
> On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <fintelia@gmail.com>
> wrote:
> >
> > The 'sfence.vma' instruction is privileged, and should only ever be
> allowed
> > when executing in supervisor mode or higher.
> >
> > Jonathan
> >
> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
>
> > ---
> > target/riscv/op_helper.c | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> > index b7dc18a41e..644d0fb35f 100644
> > --- a/target/riscv/op_helper.c
> > +++ b/target/riscv/op_helper.c
> > @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
> > {
> > RISCVCPU *cpu = riscv_env_get_cpu(env);
> > CPUState *cs = CPU(cpu);
> > - if (env->priv == PRV_S &&
> > - env->priv_ver >= PRIV_VERSION_1_10_0 &&
> > - get_field(env->mstatus, MSTATUS_TVM)) {
> > + if (!(env->priv >= PRV_S) ||
> > + (env->priv == PRV_S &&
> > + env->priv_ver >= PRIV_VERSION_1_10_0 &&
> > + get_field(env->mstatus, MSTATUS_TVM))) {
> > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> > } else {
> > tlb_flush(cs);
> > --
> > 2.20.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-12 21:14 ` Jonathan Behrens
2019-04-12 21:14 ` Jonathan Behrens
@ 2019-04-12 21:23 ` Alistair Francis
2019-04-12 21:23 ` Alistair Francis
2019-04-12 21:48 ` Palmer Dabbelt
1 sibling, 2 replies; 9+ messages in thread
From: Alistair Francis @ 2019-04-12 21:23 UTC (permalink / raw)
To: Jonathan Behrens
Cc: qemu-devel@nongnu.org Developers, Bastian Koppelmann,
Palmer Dabbelt, Alistair Francis, open list:RISC-V,
Sagar Karandikar
On Fri, Apr 12, 2019 at 2:15 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>
> Just to double check, nothing further on this is need from me, right? It is set to be merged onto the master branch once the 4.0 release is out?
Thanks for checking!
Yep you don't need to do anything, Palmer will merge it in the next
RISC-V PR after 4.0.
Alistair
>
> Jonathan
>
> On Wed, Apr 3, 2019 at 7:11 PM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>> >
>> > The 'sfence.vma' instruction is privileged, and should only ever be allowed
>> > when executing in supervisor mode or higher.
>> >
>> > Jonathan
>> >
>> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
>>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>>
>> Alistair
>>
>> > ---
>> > target/riscv/op_helper.c | 7 ++++---
>> > 1 file changed, 4 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>> > index b7dc18a41e..644d0fb35f 100644
>> > --- a/target/riscv/op_helper.c
>> > +++ b/target/riscv/op_helper.c
>> > @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
>> > {
>> > RISCVCPU *cpu = riscv_env_get_cpu(env);
>> > CPUState *cs = CPU(cpu);
>> > - if (env->priv == PRV_S &&
>> > - env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> > - get_field(env->mstatus, MSTATUS_TVM)) {
>> > + if (!(env->priv >= PRV_S) ||
>> > + (env->priv == PRV_S &&
>> > + env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> > + get_field(env->mstatus, MSTATUS_TVM))) {
>> > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> > } else {
>> > tlb_flush(cs);
>> > --
>> > 2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-12 21:23 ` Alistair Francis
@ 2019-04-12 21:23 ` Alistair Francis
2019-04-12 21:48 ` Palmer Dabbelt
1 sibling, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2019-04-12 21:23 UTC (permalink / raw)
To: Jonathan Behrens
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Fri, Apr 12, 2019 at 2:15 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>
> Just to double check, nothing further on this is need from me, right? It is set to be merged onto the master branch once the 4.0 release is out?
Thanks for checking!
Yep you don't need to do anything, Palmer will merge it in the next
RISC-V PR after 4.0.
Alistair
>
> Jonathan
>
> On Wed, Apr 3, 2019 at 7:11 PM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>> >
>> > The 'sfence.vma' instruction is privileged, and should only ever be allowed
>> > when executing in supervisor mode or higher.
>> >
>> > Jonathan
>> >
>> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
>>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>>
>> Alistair
>>
>> > ---
>> > target/riscv/op_helper.c | 7 ++++---
>> > 1 file changed, 4 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>> > index b7dc18a41e..644d0fb35f 100644
>> > --- a/target/riscv/op_helper.c
>> > +++ b/target/riscv/op_helper.c
>> > @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
>> > {
>> > RISCVCPU *cpu = riscv_env_get_cpu(env);
>> > CPUState *cs = CPU(cpu);
>> > - if (env->priv == PRV_S &&
>> > - env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> > - get_field(env->mstatus, MSTATUS_TVM)) {
>> > + if (!(env->priv >= PRV_S) ||
>> > + (env->priv == PRV_S &&
>> > + env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> > + get_field(env->mstatus, MSTATUS_TVM))) {
>> > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> > } else {
>> > tlb_flush(cs);
>> > --
>> > 2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-12 21:23 ` Alistair Francis
2019-04-12 21:23 ` Alistair Francis
@ 2019-04-12 21:48 ` Palmer Dabbelt
2019-04-12 21:48 ` Palmer Dabbelt
1 sibling, 1 reply; 9+ messages in thread
From: Palmer Dabbelt @ 2019-04-12 21:48 UTC (permalink / raw)
To: alistair23
Cc: fintelia, qemu-devel, Bastian Koppelmann, Alistair Francis,
qemu-riscv, sagark
I actually missed this. I just added it to for-next on
github.com/palmer-dabbelt.
Thanks for the ping!
On Fri, 12 Apr 2019 14:23:42 PDT (-0700), alistair23@gmail.com wrote:
> On Fri, Apr 12, 2019 at 2:15 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>>
>> Just to double check, nothing further on this is need from me, right? It is set to be merged onto the master branch once the 4.0 release is out?
>
> Thanks for checking!
>
> Yep you don't need to do anything, Palmer will merge it in the next
> RISC-V PR after 4.0.
>
> Alistair
>
>>
>> Jonathan
>>
>> On Wed, Apr 3, 2019 at 7:11 PM Alistair Francis <alistair23@gmail.com> wrote:
>>>
>>> On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>>> >
>>> > The 'sfence.vma' instruction is privileged, and should only ever be allowed
>>> > when executing in supervisor mode or higher.
>>> >
>>> > Jonathan
>>> >
>>> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
>>>
>>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>>>
>>> Alistair
>>>
>>> > ---
>>> > target/riscv/op_helper.c | 7 ++++---
>>> > 1 file changed, 4 insertions(+), 3 deletions(-)
>>> >
>>> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>>> > index b7dc18a41e..644d0fb35f 100644
>>> > --- a/target/riscv/op_helper.c
>>> > +++ b/target/riscv/op_helper.c
>>> > @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
>>> > {
>>> > RISCVCPU *cpu = riscv_env_get_cpu(env);
>>> > CPUState *cs = CPU(cpu);
>>> > - if (env->priv == PRV_S &&
>>> > - env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>> > - get_field(env->mstatus, MSTATUS_TVM)) {
>>> > + if (!(env->priv >= PRV_S) ||
>>> > + (env->priv == PRV_S &&
>>> > + env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>> > + get_field(env->mstatus, MSTATUS_TVM))) {
>>> > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>> > } else {
>>> > tlb_flush(cs);
>>> > --
>>> > 2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode
2019-04-12 21:48 ` Palmer Dabbelt
@ 2019-04-12 21:48 ` Palmer Dabbelt
0 siblings, 0 replies; 9+ messages in thread
From: Palmer Dabbelt @ 2019-04-12 21:48 UTC (permalink / raw)
To: alistair23
Cc: qemu-riscv, sagark, Bastian Koppelmann, fintelia, qemu-devel,
Alistair Francis
I actually missed this. I just added it to for-next on
github.com/palmer-dabbelt.
Thanks for the ping!
On Fri, 12 Apr 2019 14:23:42 PDT (-0700), alistair23@gmail.com wrote:
> On Fri, Apr 12, 2019 at 2:15 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>>
>> Just to double check, nothing further on this is need from me, right? It is set to be merged onto the master branch once the 4.0 release is out?
>
> Thanks for checking!
>
> Yep you don't need to do anything, Palmer will merge it in the next
> RISC-V PR after 4.0.
>
> Alistair
>
>>
>> Jonathan
>>
>> On Wed, Apr 3, 2019 at 7:11 PM Alistair Francis <alistair23@gmail.com> wrote:
>>>
>>> On Mon, Apr 1, 2019 at 1:39 PM Jonathan Behrens <fintelia@gmail.com> wrote:
>>> >
>>> > The 'sfence.vma' instruction is privileged, and should only ever be allowed
>>> > when executing in supervisor mode or higher.
>>> >
>>> > Jonathan
>>> >
>>> > Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
>>>
>>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>>>
>>> Alistair
>>>
>>> > ---
>>> > target/riscv/op_helper.c | 7 ++++---
>>> > 1 file changed, 4 insertions(+), 3 deletions(-)
>>> >
>>> > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>>> > index b7dc18a41e..644d0fb35f 100644
>>> > --- a/target/riscv/op_helper.c
>>> > +++ b/target/riscv/op_helper.c
>>> > @@ -145,9 +145,10 @@ void helper_tlb_flush(CPURISCVState *env)
>>> > {
>>> > RISCVCPU *cpu = riscv_env_get_cpu(env);
>>> > CPUState *cs = CPU(cpu);
>>> > - if (env->priv == PRV_S &&
>>> > - env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>> > - get_field(env->mstatus, MSTATUS_TVM)) {
>>> > + if (!(env->priv >= PRV_S) ||
>>> > + (env->priv == PRV_S &&
>>> > + env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>> > + get_field(env->mstatus, MSTATUS_TVM))) {
>>> > riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>> > } else {
>>> > tlb_flush(cs);
>>> > --
>>> > 2.20.1
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-04-12 21:49 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2019-04-01 19:12 [Qemu-devel] [PATCH] target/riscv: Do not allow sfence.vma from user mode Jonathan Behrens
2019-04-02 0:25 ` Richard Henderson
2019-04-03 23:10 ` Alistair Francis
2019-04-12 21:14 ` Jonathan Behrens
2019-04-12 21:14 ` Jonathan Behrens
2019-04-12 21:23 ` Alistair Francis
2019-04-12 21:23 ` Alistair Francis
2019-04-12 21:48 ` Palmer Dabbelt
2019-04-12 21:48 ` Palmer Dabbelt
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