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Tue, 06 Dec 2022 20:31:08 -0800 (PST) MIME-Version: 1.0 References: <20221201140811.142123-1-bmeng@tinylab.org> <20221201140811.142123-9-bmeng@tinylab.org> In-Reply-To: <20221201140811.142123-9-bmeng@tinylab.org> From: Alistair Francis Date: Wed, 7 Dec 2022 14:30:41 +1000 Message-ID: Subject: Re: [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC To: Bin Meng Cc: Alistair Francis , qemu-devel@nongnu.org, Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2d; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Dec 2, 2022 at 12:11 AM Bin Meng wrote: > > Per chapter 6.5.2 in [1], the number of interupt sources including > interrupt source 0 should be 187. > > [1] PolarFire SoC MSS TRM: > https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf > > Fixes: 56f6e31e7b7e ("hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board") > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > include/hw/riscv/microchip_pfsoc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h > index a757b240e0..9720bac2d5 100644 > --- a/include/hw/riscv/microchip_pfsoc.h > +++ b/include/hw/riscv/microchip_pfsoc.h > @@ -150,7 +150,7 @@ enum { > #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 > #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 > > -#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 > +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 187 > #define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 > #define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 > #define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 > -- > 2.34.1 > >