* [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes
@ 2025-10-28 8:50 frank.chang
2025-10-28 9:09 ` Jim Shu
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: frank.chang @ 2025-10-28 8:50 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
According to the RISC-V IOMMU specification:
* When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "All
inbound transactions disallowed" fault (cause = 256) is reported for any
inbound transaction.
* When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the
translated address is the same as the IOVA, unless the transaction type
is disallowed (cause = 260).
In the current implementation, the DDT cache is incorrectly looked up
even when ddtp.iommu_mode is set to Off or Bare. This may result in
unintended cache hits.
Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is
set to Off or Bare. For other modes, software is required to issue cache
invalidation commands before any inbound transactions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
hw/riscv/riscv-iommu.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index b33c7fe3259..95db811f125 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -1290,13 +1290,18 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
.devid = devid,
.process_id = process_id,
};
+ unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
ctx_cache = g_hash_table_ref(s->ctx_cache);
- ctx = g_hash_table_lookup(ctx_cache, &key);
- if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
- *ref = ctx_cache;
- return ctx;
+ if (mode != RISCV_IOMMU_DDTP_MODE_OFF &&
+ mode != RISCV_IOMMU_DDTP_MODE_BARE) {
+ ctx = g_hash_table_lookup(ctx_cache, &key);
+
+ if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
+ *ref = ctx_cache;
+ return ctx;
+ }
}
ctx = g_new0(RISCVIOMMUContext, 1);
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes
2025-10-28 8:50 [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes frank.chang
@ 2025-10-28 9:09 ` Jim Shu
2025-10-30 14:23 ` Daniel Henrique Barboza
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Jim Shu @ 2025-10-28 9:09 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
Reviewed-by: Jim Shu <jim.shu@sifive.com>
- Jim
On Tue, Oct 28, 2025 at 4:51 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> According to the RISC-V IOMMU specification:
>
> * When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "All
> inbound transactions disallowed" fault (cause = 256) is reported for any
> inbound transaction.
>
> * When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the
> translated address is the same as the IOVA, unless the transaction type
> is disallowed (cause = 260).
>
> In the current implementation, the DDT cache is incorrectly looked up
> even when ddtp.iommu_mode is set to Off or Bare. This may result in
> unintended cache hits.
>
> Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is
> set to Off or Bare. For other modes, software is required to issue cache
> invalidation commands before any inbound transactions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> hw/riscv/riscv-iommu.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index b33c7fe3259..95db811f125 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1290,13 +1290,18 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
> .devid = devid,
> .process_id = process_id,
> };
> + unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
>
> ctx_cache = g_hash_table_ref(s->ctx_cache);
> - ctx = g_hash_table_lookup(ctx_cache, &key);
>
> - if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> - *ref = ctx_cache;
> - return ctx;
> + if (mode != RISCV_IOMMU_DDTP_MODE_OFF &&
> + mode != RISCV_IOMMU_DDTP_MODE_BARE) {
> + ctx = g_hash_table_lookup(ctx_cache, &key);
> +
> + if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> + *ref = ctx_cache;
> + return ctx;
> + }
> }
>
> ctx = g_new0(RISCVIOMMUContext, 1);
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes
2025-10-28 8:50 [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes frank.chang
2025-10-28 9:09 ` Jim Shu
@ 2025-10-30 14:23 ` Daniel Henrique Barboza
2025-11-12 1:10 ` Alistair Francis
2025-11-12 1:27 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Daniel Henrique Barboza @ 2025-10-30 14:23 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs
On 10/28/25 5:50 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> According to the RISC-V IOMMU specification:
>
> * When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "All
> inbound transactions disallowed" fault (cause = 256) is reported for any
> inbound transaction.
>
> * When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the
> translated address is the same as the IOVA, unless the transaction type
> is disallowed (cause = 260).
>
> In the current implementation, the DDT cache is incorrectly looked up
> even when ddtp.iommu_mode is set to Off or Bare. This may result in
> unintended cache hits.
>
> Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is
> set to Off or Bare. For other modes, software is required to issue cache
> invalidation commands before any inbound transactions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> hw/riscv/riscv-iommu.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index b33c7fe3259..95db811f125 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1290,13 +1290,18 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
> .devid = devid,
> .process_id = process_id,
> };
> + unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
>
> ctx_cache = g_hash_table_ref(s->ctx_cache);
> - ctx = g_hash_table_lookup(ctx_cache, &key);
>
> - if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> - *ref = ctx_cache;
> - return ctx;
> + if (mode != RISCV_IOMMU_DDTP_MODE_OFF &&
> + mode != RISCV_IOMMU_DDTP_MODE_BARE) {
> + ctx = g_hash_table_lookup(ctx_cache, &key);
> +
> + if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> + *ref = ctx_cache;
> + return ctx;
> + }
> }
>
> ctx = g_new0(RISCVIOMMUContext, 1);
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes
2025-10-28 8:50 [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes frank.chang
2025-10-28 9:09 ` Jim Shu
2025-10-30 14:23 ` Daniel Henrique Barboza
@ 2025-11-12 1:10 ` Alistair Francis
2025-11-12 1:27 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2025-11-12 1:10 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
On Tue, Oct 28, 2025 at 6:54 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> According to the RISC-V IOMMU specification:
>
> * When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "All
> inbound transactions disallowed" fault (cause = 256) is reported for any
> inbound transaction.
>
> * When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the
> translated address is the same as the IOVA, unless the transaction type
> is disallowed (cause = 260).
>
> In the current implementation, the DDT cache is incorrectly looked up
> even when ddtp.iommu_mode is set to Off or Bare. This may result in
> unintended cache hits.
>
> Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is
> set to Off or Bare. For other modes, software is required to issue cache
> invalidation commands before any inbound transactions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/riscv-iommu.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index b33c7fe3259..95db811f125 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1290,13 +1290,18 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
> .devid = devid,
> .process_id = process_id,
> };
> + unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
>
> ctx_cache = g_hash_table_ref(s->ctx_cache);
> - ctx = g_hash_table_lookup(ctx_cache, &key);
>
> - if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> - *ref = ctx_cache;
> - return ctx;
> + if (mode != RISCV_IOMMU_DDTP_MODE_OFF &&
> + mode != RISCV_IOMMU_DDTP_MODE_BARE) {
> + ctx = g_hash_table_lookup(ctx_cache, &key);
> +
> + if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> + *ref = ctx_cache;
> + return ctx;
> + }
> }
>
> ctx = g_new0(RISCVIOMMUContext, 1);
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes
2025-10-28 8:50 [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes frank.chang
` (2 preceding siblings ...)
2025-11-12 1:10 ` Alistair Francis
@ 2025-11-12 1:27 ` Alistair Francis
3 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2025-11-12 1:27 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
On Tue, Oct 28, 2025 at 6:54 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> According to the RISC-V IOMMU specification:
>
> * When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "All
> inbound transactions disallowed" fault (cause = 256) is reported for any
> inbound transaction.
>
> * When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the
> translated address is the same as the IOVA, unless the transaction type
> is disallowed (cause = 260).
>
> In the current implementation, the DDT cache is incorrectly looked up
> even when ddtp.iommu_mode is set to Off or Bare. This may result in
> unintended cache hits.
>
> Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is
> set to Off or Bare. For other modes, software is required to issue cache
> invalidation commands before any inbound transactions.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/riscv/riscv-iommu.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
> index b33c7fe3259..95db811f125 100644
> --- a/hw/riscv/riscv-iommu.c
> +++ b/hw/riscv/riscv-iommu.c
> @@ -1290,13 +1290,18 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIOMMUState *s,
> .devid = devid,
> .process_id = process_id,
> };
> + unsigned mode = get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE);
>
> ctx_cache = g_hash_table_ref(s->ctx_cache);
> - ctx = g_hash_table_lookup(ctx_cache, &key);
>
> - if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> - *ref = ctx_cache;
> - return ctx;
> + if (mode != RISCV_IOMMU_DDTP_MODE_OFF &&
> + mode != RISCV_IOMMU_DDTP_MODE_BARE) {
> + ctx = g_hash_table_lookup(ctx_cache, &key);
> +
> + if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) {
> + *ref = ctx_cache;
> + return ctx;
> + }
> }
>
> ctx = g_new0(RISCVIOMMUContext, 1);
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2025-10-28 8:50 [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes frank.chang
2025-10-28 9:09 ` Jim Shu
2025-10-30 14:23 ` Daniel Henrique Barboza
2025-11-12 1:10 ` Alistair Francis
2025-11-12 1:27 ` Alistair Francis
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