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Tue, 11 Nov 2025 17:11:24 -0800 (PST) MIME-Version: 1.0 References: <20251028085032.2053569-1-frank.chang@sifive.com> In-Reply-To: <20251028085032.2053569-1-frank.chang@sifive.com> From: Alistair Francis Date: Wed, 12 Nov 2025 11:10:58 +1000 X-Gm-Features: AWmQ_bmvp3zuatO051lRp3Qntw3ipKBhhci9La7qh5Hq0xl2kVMxdOO3f8jjJUg Message-ID: Subject: Re: [PATCH] hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes To: frank.chang@sifive.com Cc: qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "open list:RISC-V TCG CPUs" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=alistair23@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Oct 28, 2025 at 6:54=E2=80=AFPM wrote: > > From: Frank Chang > > According to the RISC-V IOMMU specification: > > * When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "Al= l > inbound transactions disallowed" fault (cause =3D 256) is reported for = any > inbound transaction. > > * When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the > translated address is the same as the IOVA, unless the transaction type > is disallowed (cause =3D 260). > > In the current implementation, the DDT cache is incorrectly looked up > even when ddtp.iommu_mode is set to Off or Bare. This may result in > unintended cache hits. > > Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is > set to Off or Bare. For other modes, software is required to issue cache > invalidation commands before any inbound transactions. > > Signed-off-by: Frank Chang Acked-by: Alistair Francis Alistair > --- > hw/riscv/riscv-iommu.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index b33c7fe3259..95db811f125 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -1290,13 +1290,18 @@ static RISCVIOMMUContext *riscv_iommu_ctx(RISCVIO= MMUState *s, > .devid =3D devid, > .process_id =3D process_id, > }; > + unsigned mode =3D get_field(s->ddtp, RISCV_IOMMU_DDTP_MODE); > > ctx_cache =3D g_hash_table_ref(s->ctx_cache); > - ctx =3D g_hash_table_lookup(ctx_cache, &key); > > - if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) { > - *ref =3D ctx_cache; > - return ctx; > + if (mode !=3D RISCV_IOMMU_DDTP_MODE_OFF && > + mode !=3D RISCV_IOMMU_DDTP_MODE_BARE) { > + ctx =3D g_hash_table_lookup(ctx_cache, &key); > + > + if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) { > + *ref =3D ctx_cache; > + return ctx; > + } > } > > ctx =3D g_new0(RISCVIOMMUContext, 1); > -- > 2.43.0 > >