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Wed, 25 Mar 2026 19:08:57 -0700 (PDT) MIME-Version: 1.0 References: <20260318103122.97244-1-philmd@linaro.org> <20260318103122.97244-7-philmd@linaro.org> In-Reply-To: <20260318103122.97244-7-philmd@linaro.org> From: Alistair Francis Date: Thu, 26 Mar 2026 12:08:30 +1000 X-Gm-Features: AQROBzBFyPfMOYLwMqXXk8khpnb4LbBOpiLzUluGgMq20bhdOaG3dzw-g87_Qu0 Message-ID: Subject: Re: [PATCH-for-11.1 06/16] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Weiwei Li , Pierrick Bouvier , Warner Losh , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , Vijai Kumar K , Anton Johansson , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Jiaxun Yang , Peter Maydell , Liu Zhiwei , Djordje Todorovic Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=alistair23@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 18, 2026 at 8:34=E2=80=AFPM Philippe Mathieu-Daud=C3=A9 wrote: > > All callers of gen_load_acquire() and gen_store_release() set both > the MO_ALIGN|MO_TE flags. Set them once in each callee. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 ++++++++++-------- > 1 file changed, 10 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/= insn_trans/trans_rvzalasr.c.inc > index 525f01ca347..2b1f73f650b 100644 > --- a/target/riscv/insn_trans/trans_rvzalasr.c.inc > +++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc > @@ -29,6 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_= aqrl *a, MemOp memop) > return false; > } > > + memop |=3D MO_ALIGN | MO_TE; > memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; > > tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); > @@ -43,26 +44,26 @@ static bool gen_load_acquire(DisasContext *ctx, arg_l= b_aqrl *a, MemOp memop) > static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB)); > + return gen_load_acquire(ctx, a, MO_SB); > } > > static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW)); > + return gen_load_acquire(ctx, a, MO_SW); > } > > static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); > + return gen_load_acquire(ctx, a, MO_SL); > } > > static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_ZALASR(ctx); > - return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ)); > + return gen_load_acquire(ctx, a, MO_UQ); > } > > static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp m= emop) > @@ -78,6 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb= _aqrl *a, MemOp memop) > return false; > } > > + memop |=3D MO_ALIGN | MO_TE; > memop |=3D (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0; > > /* Add a memory barrier implied by RL (mandatory) and AQ (optional) = */ > @@ -90,24 +92,24 @@ static bool gen_store_release(DisasContext *ctx, arg_= sb_aqrl *a, MemOp memop) > static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_store_release(ctx, a, (MO_ALIGN | MO_SB)); > + return gen_store_release(ctx, a, MO_SB); > } > > static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW)); > + return gen_store_release(ctx, a, MO_SW); > } > > static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a) > { > REQUIRE_ZALASR(ctx); > - return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL)); > + return gen_store_release(ctx, a, MO_SL); > } > > static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_ZALASR(ctx); > - return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ)); > + return gen_store_release(ctx, a, MO_UQ); > } > -- > 2.53.0 > >