* [PATCH qemu 1/3] hw/misc: Implement STM32L4xx SYSCFG
2023-12-10 19:05 [PATCH qemu 0/3] [PATCH qemu 0/3] hw/arm: Add device STM32L4x5 SYSCFG ~inesvarhol
@ 2023-12-10 17:51 ` ~inesvarhol
2023-12-18 3:52 ` Alistair Francis
2023-12-10 17:55 ` [PATCH qemu 2/3] tests/qtest: Add STM32L4xx SYSCFG QTest testcase ~inesvarhol
2023-12-10 18:06 ` [PATCH qemu 3/3] hw/arm: Connect STM32L4xx SYSCFG to STM32L4x5 SoC ~inesvarhol
2 siblings, 1 reply; 7+ messages in thread
From: ~inesvarhol @ 2023-12-10 17:51 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, alistair, philmd, peter.maydell, ines.varhol,
arnaud.minier
From: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/stm32l4xx_syscfg.c | 277 +++++++++++++++++++++++++++++
hw/misc/trace-events | 6 +
include/hw/misc/stm32l4xx_syscfg.h | 62 +++++++
5 files changed, 349 insertions(+)
create mode 100644 hw/misc/stm32l4xx_syscfg.c
create mode 100644 include/hw/misc/stm32l4xx_syscfg.h
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 3efe3dc2cc..a20427a9be 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -90,6 +90,9 @@ config STM32F4XX_EXTI
config STM32L4X5_EXTI
bool
+config STM32L4XX_SYSCFG
+ bool
+
config MIPS_ITU
bool
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 16db6e228d..120c59d9f4 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -111,6 +111,7 @@ system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.
system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
system_ss.add(when: 'CONFIG_STM32L4X5_EXTI', if_true: files('stm32l4x5_exti.c'))
+system_ss.add(when: 'CONFIG_STM32L4XX_SYSCFG', if_true: files('stm32l4xx_syscfg.c'))
system_ss.add(when: 'CONFIG_MPS2_FPGAIO', if_true: files('mps2-fpgaio.c'))
system_ss.add(when: 'CONFIG_MPS2_SCC', if_true: files('mps2-scc.c'))
diff --git a/hw/misc/stm32l4xx_syscfg.c b/hw/misc/stm32l4xx_syscfg.c
new file mode 100644
index 0000000000..a8ef370117
--- /dev/null
+++ b/hw/misc/stm32l4xx_syscfg.c
@@ -0,0 +1,277 @@
+/*
+ * STM32L4xx SYSCFG (System Configuration Controller)
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Based on the stm32f4xx_syscfg by Alistair Francis.
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "hw/misc/stm32l4xx_syscfg.h"
+
+#define NUM_GPIOS 7
+
+#define SYSCFG_MEMRMP 0x00
+#define SYSCFG_CFGR1 0x04
+#define SYSCFG_EXTICR1 0x08
+#define SYSCFG_EXTICR2 0x0C
+#define SYSCFG_EXTICR3 0x10
+#define SYSCFG_EXTICR4 0x14
+#define SYSCFG_SCSR 0x18
+#define SYSCFG_CFGR2 0x1C
+#define SYSCFG_SWPR 0x20
+#define SYSCFG_SKR 0x24
+#define SYSCFG_SWPR2 0x28
+
+/* 00000000_00000000_00000001_00000111 */
+#define ACTIVABLE_BITS_MEMRP 0x00000107
+
+/* 11111100_11111111_00000001_00000000 */
+#define ACTIVABLE_BITS_CFGR1 0xFCFF0100
+/* 00000000_00000000_00000000_00000001 */
+#define FIREWALL_DISABLE_CFGR1 0x00000001
+
+/* 00000000_00000000_00000000_00000001 */
+#define ACTIVABLE_BITS_EXTICR 0x0000FFFF
+
+/* 00000000_00000000_00000000_00000011 */
+/* #define ACTIVABLE_BITS_SCSR 0x00000003 */
+
+/* 00000000_00000000_00000000_00001111 */
+#define ECC_LOCK_CFGR2 0x0000000F
+/* 00000000_00000000_00000001_00000000 */
+#define SRAM2_PARITY_ERROR_FLAG_CFGR2 0x00000100
+
+/* 00000000_00000000_00000000_11111111 */
+#define ACTIVABLE_BITS_SKR 0x000000FF
+
+static void stm32l4xx_syscfg_hold_reset(Object *obj)
+{
+ STM32L4xxSyscfgState *s = STM32L4XX_SYSCFG(obj);
+
+ s->memrmp = 0x00000000;
+ s->cfgr1 = 0x7C000001;
+ s->exticr[0] = 0x00000000;
+ s->exticr[1] = 0x00000000;
+ s->exticr[2] = 0x00000000;
+ s->exticr[3] = 0x00000000;
+ s->scsr = 0x00000000;
+ s->cfgr2 = 0x00000000;
+ s->swpr = 0x00000000;
+ s->skr = 0x00000000;
+ s->swpr2 = 0x00000000;
+}
+
+static void stm32l4xx_syscfg_set_irq(void *opaque, int irq, int level)
+{
+ STM32L4xxSyscfgState *s = opaque;
+ uint8_t gpio = irq / 16;
+ g_assert(gpio < NUM_GPIOS);
+
+ int line = irq % 16;
+ int exticr_reg = line / 4;
+ int startbit = (irq % 4) * 4;
+
+ trace_stm32l4xx_syscfg_set_irq(gpio, irq % 16, level);
+
+ if (extract32(s->exticr[exticr_reg], startbit, 4) == gpio) {
+ trace_stm32l4xx_syscfg_pulse_exti(line);
+ qemu_set_irq(s->gpio_out[line], level);
+ }
+}
+
+static uint64_t stm32l4xx_syscfg_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ STM32L4xxSyscfgState *s = opaque;
+
+ trace_stm32l4xx_syscfg_read(addr);
+
+ switch (addr) {
+ case SYSCFG_MEMRMP:
+ return s->memrmp;
+ case SYSCFG_CFGR1:
+ return s->cfgr1;
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
+ return s->exticr[(addr - SYSCFG_EXTICR1) / 4];
+ case SYSCFG_SCSR:
+ return s->scsr;
+ case SYSCFG_CFGR2:
+ return s->cfgr2;
+ case SYSCFG_SWPR:
+ return s->swpr;
+ case SYSCFG_SKR:
+ return s->skr;
+ case SYSCFG_SWPR2:
+ return s->swpr2;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ return 0;
+ }
+}
+
+static void stm32l4xx_syscfg_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ STM32L4xxSyscfgState *s = opaque;
+ uint32_t value = val64;
+
+ trace_stm32l4xx_syscfg_write(value, addr);
+
+ switch (addr) {
+ case SYSCFG_MEMRMP:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Changing the memory mapping isn't supported\n",
+ __func__);
+ s->memrmp = value & ACTIVABLE_BITS_MEMRP;
+ return;
+ case SYSCFG_CFGR1:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Functions in CFGRx aren't supported\n",
+ __func__);
+ /* bit 0 (firewall dis.) is cleared by software, set only by reset. */
+ s->cfgr1 = (s->cfgr1 & value & FIREWALL_DISABLE_CFGR1) |
+ (value & ACTIVABLE_BITS_CFGR1);
+ return;
+ case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
+ s->exticr[(addr - SYSCFG_EXTICR1) / 4] =
+ (value & ACTIVABLE_BITS_EXTICR);
+ return;
+ case SYSCFG_SCSR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Erasing SRAM2 isn't supported\n",
+ __func__);
+ /*
+ * only non reserved bits are :
+ * bit 0 (write-protected by a passkey), bit 1 (meant to be read)
+ * so it serves no purpose yet to add :
+ * s->scsr = value & 0x3;
+ */
+ return;
+ case SYSCFG_CFGR2:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Functions in CFGRx aren't supported\n",
+ __func__);
+ /* bit 8 (SRAM2 PEF) is cleared by software by writing a '1'.*/
+ /* bits[3:0] (ECC Lock) are set by software, cleared only by reset.*/
+ s->cfgr2 = (s->cfgr2 | (value & ECC_LOCK_CFGR2)) &
+ ~(value & SRAM2_PARITY_ERROR_FLAG_CFGR2);
+ return;
+ case SYSCFG_SWPR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Write protecting SRAM2 isn't supported\n",
+ __func__);
+ /* These bits are set by software and cleared only by reset.*/
+ s->swpr |= value;
+ return;
+ case SYSCFG_SKR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Erasing SRAM2 isn't supported\n",
+ __func__);
+ s->skr = value & ACTIVABLE_BITS_SKR;
+ return;
+ case SYSCFG_SWPR2:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Write protecting SRAM2 isn't supported\n",
+ __func__);
+ /* These bits are set by software and cleared only by reset.*/
+ s->swpr2 |= value;
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps stm32l4xx_syscfg_ops = {
+ .read = stm32l4xx_syscfg_read,
+ .write = stm32l4xx_syscfg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .impl.unaligned = false,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .valid.unaligned = false,
+};
+
+static void stm32l4xx_syscfg_init(Object *obj)
+{
+ STM32L4xxSyscfgState *s = STM32L4XX_SYSCFG(obj);
+
+ memory_region_init_io(&s->mmio, obj, &stm32l4xx_syscfg_ops, s,
+ TYPE_STM32L4XX_SYSCFG, 0x400);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ qdev_init_gpio_in(DEVICE(obj), stm32l4xx_syscfg_set_irq, 16 * NUM_GPIOS);
+ qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
+}
+
+static const VMStateDescription vmstate_stm32l4xx_syscfg = {
+ .name = TYPE_STM32L4XX_SYSCFG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(memrmp, STM32L4xxSyscfgState),
+ VMSTATE_UINT32(cfgr1, STM32L4xxSyscfgState),
+ VMSTATE_UINT32_ARRAY(exticr, STM32L4xxSyscfgState,
+ SYSCFG_NUM_EXTICR),
+ VMSTATE_UINT32(scsr, STM32L4xxSyscfgState),
+ VMSTATE_UINT32(cfgr2, STM32L4xxSyscfgState),
+ VMSTATE_UINT32(swpr, STM32L4xxSyscfgState),
+ VMSTATE_UINT32(skr, STM32L4xxSyscfgState),
+ VMSTATE_UINT32(swpr2, STM32L4xxSyscfgState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32l4xx_syscfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ dc->vmsd = &vmstate_stm32l4xx_syscfg;
+ rc->phases.hold = stm32l4xx_syscfg_hold_reset;
+}
+
+static const TypeInfo stm32l4xx_syscfg_info[] = {
+ {
+ .name = TYPE_STM32L4XX_SYSCFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(STM32L4xxSyscfgState),
+ .instance_init = stm32l4xx_syscfg_init,
+ .class_init = stm32l4xx_syscfg_class_init,
+ }
+};
+
+DEFINE_TYPES(stm32l4xx_syscfg_info)
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 2f01c62c0e..756cb45bd6 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -163,6 +163,12 @@ stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+# stm32l4xx_syscfg.c
+stm32l4xx_syscfg_set_irq(int gpio, int line, int level) "irq from GPIO: %d, line: %d, level: %d"
+stm32l4xx_syscfg_pulse_exti(int irq) "irq %d forwarded to EXTI"
+stm32l4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
+stm32l4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+
# stm32l4x5_exti.c
stm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
stm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
diff --git a/include/hw/misc/stm32l4xx_syscfg.h b/include/hw/misc/stm32l4xx_syscfg.h
new file mode 100644
index 0000000000..d9ed4da74e
--- /dev/null
+++ b/include/hw/misc/stm32l4xx_syscfg.h
@@ -0,0 +1,62 @@
+/*
+ * STM32L4xx SYSCFG (System Configuration Controller)
+ *
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Based on the stm32f4xx_syscfg by Alistair Francis.
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#ifndef HW_STM32L4XX_SYSCFG_H
+#define HW_STM32L4XX_SYSCFG_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_STM32L4XX_SYSCFG "stm32l4xx-syscfg"
+OBJECT_DECLARE_SIMPLE_TYPE(STM32L4xxSyscfgState, STM32L4XX_SYSCFG)
+
+#define SYSCFG_NUM_EXTICR 4
+
+struct STM32L4xxSyscfgState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ uint32_t memrmp;
+ uint32_t cfgr1;
+ uint32_t exticr[SYSCFG_NUM_EXTICR];
+ uint32_t scsr;
+ uint32_t cfgr2;
+ uint32_t swpr;
+ uint32_t skr;
+ uint32_t swpr2;
+
+ qemu_irq gpio_out[16];
+};
+
+#endif
--
2.38.5
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH qemu 2/3] tests/qtest: Add STM32L4xx SYSCFG QTest testcase
2023-12-10 19:05 [PATCH qemu 0/3] [PATCH qemu 0/3] hw/arm: Add device STM32L4x5 SYSCFG ~inesvarhol
2023-12-10 17:51 ` [PATCH qemu 1/3] hw/misc: Implement STM32L4xx SYSCFG ~inesvarhol
@ 2023-12-10 17:55 ` ~inesvarhol
2023-12-18 3:53 ` Alistair Francis
2023-12-10 18:06 ` [PATCH qemu 3/3] hw/arm: Connect STM32L4xx SYSCFG to STM32L4x5 SoC ~inesvarhol
2 siblings, 1 reply; 7+ messages in thread
From: ~inesvarhol @ 2023-12-10 17:55 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, alistair, philmd, peter.maydell, ines.varhol,
arnaud.minier
From: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4xx_syscfg-test.c | 408 ++++++++++++++++++++++++++++
2 files changed, 410 insertions(+), 1 deletion(-)
create mode 100644 tests/qtest/stm32l4xx_syscfg-test.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index d5126f4d86..06a04ed17d 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -196,7 +196,8 @@ qtests_aspeed = \
'aspeed_gpio-test']
qtests_stm32l4x5 = \
- ['stm32l4x5_exti-test']
+ ['stm32l4x5_exti-test',
+ 'stm32l4xx_syscfg-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
diff --git a/tests/qtest/stm32l4xx_syscfg-test.c b/tests/qtest/stm32l4xx_syscfg-test.c
new file mode 100644
index 0000000000..166b596ba6
--- /dev/null
+++ b/tests/qtest/stm32l4xx_syscfg-test.c
@@ -0,0 +1,408 @@
+/*
+ * QTest testcase for STM32L4xx_SYSCFG
+ *
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+#define SYSCFG_BASE_ADDR 0x40010000
+#define SYSCFG_MEMRMP 0x00
+#define SYSCFG_CFGR1 0x04
+#define SYSCFG_EXTICR1 0x08
+#define SYSCFG_EXTICR2 0x0C
+#define SYSCFG_EXTICR3 0x10
+#define SYSCFG_EXTICR4 0x14
+#define SYSCFG_SCSR 0x18
+#define SYSCFG_CFGR2 0x1C
+#define SYSCFG_SWPR 0x20
+#define SYSCFG_SKR 0x24
+#define SYSCFG_SWPR2 0x28
+#define INVALID_ADDR 0x2C
+
+#define EXTI_BASE_ADDR 0x40010400
+#define EXTI_IMR1 0x00
+#define EXTI_RTSR1 0x08
+#define EXTI_FTSR1 0x0C
+
+static void syscfg_writel(unsigned int offset, uint32_t value)
+{
+ writel(SYSCFG_BASE_ADDR + offset, value);
+}
+
+static uint32_t syscfg_readl(unsigned int offset)
+{
+ return readl(SYSCFG_BASE_ADDR + offset);
+}
+
+static void exti_writel(unsigned int offset, uint32_t value)
+{
+ writel(EXTI_BASE_ADDR + offset, value);
+}
+
+static void system_reset(void)
+{
+ QDict *response;
+ response = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
+ g_assert(qdict_haskey(response, "return"));
+ qobject_unref(response);
+}
+
+static void test_reset(void)
+{
+ /*
+ * Test that registers are initialized at the correct values
+ */
+ const uint32_t memrmp = syscfg_readl(SYSCFG_MEMRMP);
+ g_assert_cmpuint(memrmp, ==, 0x00000000);
+
+ const uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
+ g_assert_cmpuint(cfgr1, ==, 0x7C000001);
+
+ const uint32_t exticr1 = syscfg_readl(SYSCFG_EXTICR1);
+ g_assert_cmpuint(exticr1, ==, 0x00000000);
+
+ const uint32_t exticr2 = syscfg_readl(SYSCFG_EXTICR2);
+ g_assert_cmpuint(exticr2, ==, 0x00000000);
+
+ const uint32_t exticr3 = syscfg_readl(SYSCFG_EXTICR3);
+ g_assert_cmpuint(exticr3, ==, 0x00000000);
+
+ const uint32_t exticr4 = syscfg_readl(SYSCFG_EXTICR4);
+ g_assert_cmpuint(exticr4, ==, 0x00000000);
+
+ const uint32_t scsr = syscfg_readl(SYSCFG_SCSR);
+ g_assert_cmpuint(scsr, ==, 0x00000000);
+
+ const uint32_t cfgr2 = syscfg_readl(SYSCFG_CFGR2);
+ g_assert_cmpuint(cfgr2, ==, 0x00000000);
+
+ const uint32_t swpr = syscfg_readl(SYSCFG_SWPR);
+ g_assert_cmpuint(swpr, ==, 0x00000000);
+
+ const uint32_t skr = syscfg_readl(SYSCFG_SKR);
+ g_assert_cmpuint(skr, ==, 0x00000000);
+
+ const uint32_t swpr2 = syscfg_readl(SYSCFG_SWPR2);
+ g_assert_cmpuint(swpr2, ==, 0x00000000);
+}
+
+static void test_reserved_bits(void)
+{
+ /*
+ * Test that reserved bits stay at reset value
+ * (which is 0 for all of them) by writing '1'
+ * in all reserved bits (keeping reset value for
+ * other bits) and checking that the
+ * register is still at reset value
+ */
+ syscfg_writel(SYSCFG_MEMRMP, 0xFFFFFEF8);
+ const uint32_t memrmp = syscfg_readl(SYSCFG_MEMRMP);
+ g_assert_cmpuint(memrmp, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_CFGR1, 0x7F00FEFF);
+ const uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
+ g_assert_cmpuint(cfgr1, ==, 0x7C000001);
+
+ syscfg_writel(SYSCFG_EXTICR1, 0xFFFF0000);
+ const uint32_t exticr1 = syscfg_readl(SYSCFG_EXTICR1);
+ g_assert_cmpuint(exticr1, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR2, 0xFFFF0000);
+ const uint32_t exticr2 = syscfg_readl(SYSCFG_EXTICR2);
+ g_assert_cmpuint(exticr2, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR3, 0xFFFF0000);
+ const uint32_t exticr3 = syscfg_readl(SYSCFG_EXTICR3);
+ g_assert_cmpuint(exticr3, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR4, 0xFFFF0000);
+ const uint32_t exticr4 = syscfg_readl(SYSCFG_EXTICR4);
+ g_assert_cmpuint(exticr4, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_SKR, 0xFFFFFF00);
+ const uint32_t skr = syscfg_readl(SYSCFG_SKR);
+ g_assert_cmpuint(skr, ==, 0x00000000);
+}
+
+static void test_set_and_clear(void)
+{
+ /*
+ * Test that regular bits can be set and cleared
+ */
+ syscfg_writel(SYSCFG_MEMRMP, 0x00000107);
+ uint32_t memrmp = syscfg_readl(SYSCFG_MEMRMP);
+ g_assert_cmpuint(memrmp, ==, 0x00000107);
+ syscfg_writel(SYSCFG_MEMRMP, 0x00000000);
+ memrmp = syscfg_readl(SYSCFG_MEMRMP);
+ g_assert_cmpuint(memrmp, ==, 0x00000000);
+
+ /* cfgr1 bit 0 is clear only so we keep it set */
+ syscfg_writel(SYSCFG_CFGR1, 0xFCFF0101);
+ uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
+ g_assert_cmpuint(cfgr1, ==, 0xFCFF0101);
+ syscfg_writel(SYSCFG_CFGR1, 0x00000001);
+ cfgr1 = syscfg_readl(SYSCFG_CFGR1);
+ g_assert_cmpuint(cfgr1, ==, 0x00000001);
+
+ syscfg_writel(SYSCFG_EXTICR1, 0x0000FFFF);
+ uint32_t exticr1 = syscfg_readl(SYSCFG_EXTICR1);
+ g_assert_cmpuint(exticr1, ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
+ exticr1 = syscfg_readl(SYSCFG_EXTICR1);
+ g_assert_cmpuint(exticr1, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR2, 0x0000FFFF);
+ uint32_t exticr2 = syscfg_readl(SYSCFG_EXTICR2);
+ g_assert_cmpuint(exticr2, ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR2, 0x00000000);
+ exticr2 = syscfg_readl(SYSCFG_EXTICR2);
+ g_assert_cmpuint(exticr2, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR3, 0x0000FFFF);
+ uint32_t exticr3 = syscfg_readl(SYSCFG_EXTICR3);
+ g_assert_cmpuint(exticr3, ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR3, 0x00000000);
+ exticr3 = syscfg_readl(SYSCFG_EXTICR3);
+ g_assert_cmpuint(exticr3, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_EXTICR4, 0x0000FFFF);
+ uint32_t exticr4 = syscfg_readl(SYSCFG_EXTICR4);
+ g_assert_cmpuint(exticr4, ==, 0x0000FFFF);
+ syscfg_writel(SYSCFG_EXTICR4, 0x00000000);
+ exticr4 = syscfg_readl(SYSCFG_EXTICR4);
+ g_assert_cmpuint(exticr4, ==, 0x00000000);
+
+ syscfg_writel(SYSCFG_SKR, 0x000000FF);
+ uint32_t skr = syscfg_readl(SYSCFG_SKR);
+ g_assert_cmpuint(skr, ==, 0x000000FF);
+ syscfg_writel(SYSCFG_SKR, 0x00000000);
+ skr = syscfg_readl(SYSCFG_SKR);
+ g_assert_cmpuint(skr, ==, 0x00000000);
+}
+
+static void test_clear_by_writing_1(void)
+{
+ /*
+ * Test that writing '1' doesn't set the bit
+ */
+ syscfg_writel(SYSCFG_CFGR2, 0x00000100);
+ const uint32_t cfgr2 = syscfg_readl(SYSCFG_CFGR2);
+ g_assert_cmpuint(cfgr2, ==, 0x00000000);
+}
+
+static void test_set_only_bits(void)
+{
+ /*
+ * Test that set only bits stay can't be cleared
+ */
+ syscfg_writel(SYSCFG_CFGR2, 0x0000000F);
+ syscfg_writel(SYSCFG_CFGR2, 0x00000000);
+ const uint32_t exticr3 = syscfg_readl(SYSCFG_CFGR2);
+ g_assert_cmpuint(exticr3, ==, 0x0000000F);
+
+ syscfg_writel(SYSCFG_SWPR, 0xFFFFFFFF);
+ syscfg_writel(SYSCFG_SWPR, 0x00000000);
+ const uint32_t swpr = syscfg_readl(SYSCFG_SWPR);
+ g_assert_cmpuint(swpr, ==, 0xFFFFFFFF);
+
+ syscfg_writel(SYSCFG_SWPR2, 0xFFFFFFFF);
+ syscfg_writel(SYSCFG_SWPR2, 0x00000000);
+ const uint32_t swpr2 = syscfg_readl(SYSCFG_SWPR2);
+ g_assert_cmpuint(swpr2, ==, 0xFFFFFFFF);
+
+ system_reset();
+}
+
+static void test_clear_only_bits(void)
+{
+ /*
+ * Test that clear only bits stay can't be set
+ */
+ syscfg_writel(SYSCFG_CFGR1, 0x00000000);
+ syscfg_writel(SYSCFG_CFGR1, 0x00000001);
+ const uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
+ g_assert_cmpuint(cfgr1, ==, 0x00000000);
+
+ system_reset();
+}
+
+static void test_interrupt(void)
+{
+ /*
+ * Test that GPIO rising lines result in an irq
+ * with the right configuration
+ */
+ qtest_irq_intercept_in(global_qtest, "/machine/unattached/device[0]/exti");
+ /* Enable interrupt on rising edge of GPIO PA[0] */
+ exti_writel(EXTI_IMR1, 0x00000001);
+ exti_writel(EXTI_RTSR1, 0x00000001);
+
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 1);
+
+ g_assert_true(get_irq(0));
+
+ /* Enable interrupt on rising edge of GPIO PA[15] */
+ exti_writel(EXTI_IMR1, 0x00008000);
+ exti_writel(EXTI_RTSR1, 0x00008000);
+
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 15, 1);
+
+ g_assert_true(get_irq(15));
+
+ /* Enable interrupt on rising edge of GPIO PB[1] */
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000010);
+ exti_writel(EXTI_IMR1, 0x00000002);
+ exti_writel(EXTI_RTSR1, 0x00000002);
+
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 17, 1);
+
+ g_assert_true(get_irq(1));
+
+ /* Clean the test */
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 0);
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 15, 0);
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 17, 0);
+}
+
+static void test_irq_pin_multiplexer(void)
+{
+ /*
+ * Test that syscfg irq sets the right exti irq
+ */
+
+ qtest_irq_intercept_in(global_qtest, "/machine/unattached/device[0]/exti");
+
+ /* Enable interrupt on rising edge of GPIO PA[0] */
+ exti_writel(EXTI_IMR1, 0x00000001);
+ exti_writel(EXTI_RTSR1, 0x00000001);
+
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 1);
+
+ /* Check that irq 0 was set and irq 15 wasn't */
+ g_assert_true(get_irq(0));
+ g_assert_false(get_irq(15));
+
+ /* Clean the test */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 0);
+
+ /* Enable interrupt on rising edge of GPIO PA[15] */
+ exti_writel(EXTI_IMR1, 0x00008000);
+ exti_writel(EXTI_RTSR1, 0x00008000);
+
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 15, 1);
+
+ /* Check that irq 15 was set and irq 0 wasn't */
+ g_assert_true(get_irq(15));
+ g_assert_false(get_irq(0));
+
+ /* Clean the test */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 15, 0);
+}
+
+static void test_irq_gpio_multiplexer(void)
+{
+ /*
+ * Test that an irq is generated only by the right GPIO
+ */
+
+ qtest_irq_intercept_in(global_qtest, "/machine/unattached/device[0]/exti");
+
+ /* Enable interrupt on rising edge of GPIO PA[0] */
+ exti_writel(EXTI_IMR1, 0x00000001);
+ exti_writel(EXTI_RTSR1, 0x00000001);
+
+ /* Check that setting rising pin GPIOA[0] generates an irq */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 1);
+
+ g_assert_true(get_irq(0));
+
+ /* Clean the test */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 0);
+
+ /* Check that setting rising pin GPIOB[0] doesn't generate an irq */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 16, 1);
+
+ g_assert_false(get_irq(0));
+
+ /* Clean the test */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 16, 0);
+
+ /* Enable interrupt on rising edge of GPIO PB[0] */
+ exti_writel(EXTI_IMR1, 0x00000001);
+ exti_writel(EXTI_RTSR1, 0x00000001);
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000001);
+
+ /* Check that setting rising pin GPIOA[0] doesn't generate an irq */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 1);
+
+ g_assert_false(get_irq(0));
+
+ /* Clean the test */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 0, 0);
+
+ /* Check that setting rising pin GPIOB[0] generates an irq */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 16, 1);
+
+ g_assert_true(get_irq(0));
+
+ /* Clean the test */
+ qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
+ NULL, 16, 0);
+ syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+ g_test_set_nonfatal_assertions();
+
+ qtest_add_func("stm32l4x5/syscfg/test_reset", test_reset);
+ qtest_add_func("stm32l4x5/syscfg/test_reserved_bits",
+ test_reserved_bits);
+ qtest_add_func("stm32l4x5/syscfg/test_set_and_clear",
+ test_set_and_clear);
+ qtest_add_func("stm32l4x5/syscfg/test_clear_by_writing_1",
+ test_clear_by_writing_1);
+ qtest_add_func("stm32l4x5/syscfg/test_set_only_bits",
+ test_set_only_bits);
+ qtest_add_func("stm32l4x5/syscfg/test_clear_only_bits",
+ test_clear_only_bits);
+ qtest_add_func("stm32l4x5/syscfg/test_interrupt",
+ test_interrupt);
+ qtest_add_func("stm32l4x5/syscfg/test_irq_pin_multiplexer",
+ test_irq_pin_multiplexer);
+ qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer",
+ test_irq_gpio_multiplexer);
+
+ qtest_start("-machine b-l475e-iot01a");
+ ret = g_test_run();
+ qtest_end();
+
+ return ret;
+}
--
2.38.5
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH qemu 3/3] hw/arm: Connect STM32L4xx SYSCFG to STM32L4x5 SoC
2023-12-10 19:05 [PATCH qemu 0/3] [PATCH qemu 0/3] hw/arm: Add device STM32L4x5 SYSCFG ~inesvarhol
2023-12-10 17:51 ` [PATCH qemu 1/3] hw/misc: Implement STM32L4xx SYSCFG ~inesvarhol
2023-12-10 17:55 ` [PATCH qemu 2/3] tests/qtest: Add STM32L4xx SYSCFG QTest testcase ~inesvarhol
@ 2023-12-10 18:06 ` ~inesvarhol
2023-12-18 3:57 ` Alistair Francis
2 siblings, 1 reply; 7+ messages in thread
From: ~inesvarhol @ 2023-12-10 18:06 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, alistair, philmd, peter.maydell, ines.varhol,
arnaud.minier
From: Inès Varhol <ines.varhol@telecom-paris.fr>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
---
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 24 ++++++++++++++++--------
include/hw/arm/stm32l4x5_soc.h | 2 ++
3 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 9c9d5bb541..ea77977d4b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -458,6 +458,7 @@ config STM32L4X5_SOC
bool
select ARM_V7M
select OR_IRQ
+ select STM32L4XX_SYSCFG
select STM32L4X5_EXTI
config XLNX_ZYNQMP_ARM
diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
index cf786eac1d..9b45a9e606 100644
--- a/hw/arm/stm32l4x5_soc.c
+++ b/hw/arm/stm32l4x5_soc.c
@@ -46,6 +46,7 @@
#define SRAM2_SIZE (32 * KiB)
#define EXTI_ADDR 0x40010400
+#define SYSCFG_ADDR 0x40010000
#define NUM_EXTI_IRQ 40
/* Match exti line connections with their CPU IRQ number */
@@ -90,6 +91,8 @@ static void stm32l4x5_soc_initfn(Object *obj)
object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
+ object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4XX_SYSCFG);
+
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
}
@@ -167,6 +170,15 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ /* System configuration controller */
+ dev = DEVICE(&s->syscfg);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
+
+ /* EXTI device */
dev = DEVICE(&s->exti);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) {
return;
@@ -178,13 +190,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
}
- /*
- * Uncomment when Syscfg is implemented
- * for (i = 0; i < 16; i++) {
- * qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
- * qdev_get_gpio_in(dev, i));
- * }
- */
+ for (i = 0; i < 16; i++) {
+ qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
+ qdev_get_gpio_in(dev, i));
+ }
/* APB1 BUS */
create_unimplemented_device("TIM2", 0x40000000, 0x400);
@@ -223,7 +232,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
/* RESERVED: 0x40009800, 0x6800 */
/* APB2 BUS */
- create_unimplemented_device("SYSCFG", 0x40010000, 0x30);
create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0);
create_unimplemented_device("COMP", 0x40010200, 0x200);
/* RESERVED: 0x40010800, 0x1400 */
diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
index ac47158596..5ff757f15b 100644
--- a/include/hw/arm/stm32l4x5_soc.h
+++ b/include/hw/arm/stm32l4x5_soc.h
@@ -37,6 +37,7 @@
#include "qemu/units.h"
#include "hw/qdev-core.h"
#include "hw/arm/armv7m.h"
+#include "hw/misc/stm32l4xx_syscfg.h"
#include "hw/misc/stm32l4x5_exti.h"
#include "qom/object.h"
@@ -52,6 +53,7 @@ struct Stm32l4x5SocState {
ARMv7MState armv7m;
Stm32l4x5ExtiState exti;
+ STM32L4xxSyscfgState syscfg;
MemoryRegion sram1;
MemoryRegion sram2;
--
2.38.5
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH qemu 0/3] [PATCH qemu 0/3] hw/arm: Add device STM32L4x5 SYSCFG
@ 2023-12-10 19:05 ~inesvarhol
2023-12-10 17:51 ` [PATCH qemu 1/3] hw/misc: Implement STM32L4xx SYSCFG ~inesvarhol
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: ~inesvarhol @ 2023-12-10 19:05 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, alistair, philmd, peter.maydell, ines.varhol,
arnaud.minier
This patch adds a new SYSCFG peripheral used by the STM32L4x5 SoC.
The implementation is inspired from the STM32F4xx SYSCFG, the device
registers however aren't the same.
The patch is split up in 3 commits :
- implementing the SYSCFG device
- adding tests (that fail in this commit)
- connecting the SYSCFG device to the SoC (the tests pass in this
commit)
Based-on: <170198462199.32162.284497577253427308-0@git.sr.ht>
([PATCH qemu 0/3] hw/arm: Add device STM32L4x5 EXTI)
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Inès Varhol (3):
hw/misc: Implement STM32L4xx SYSCFG
tests/qtest: Add STM32L4xx SYSCFG QTest testcase
hw/arm: Connect STM32L4xx SYSCFG to STM32L4x5 SoC
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 24 +-
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
hw/misc/stm32l4xx_syscfg.c | 277 +++++++++++++++++++
hw/misc/trace-events | 6 +
include/hw/arm/stm32l4x5_soc.h | 2 +
include/hw/misc/stm32l4xx_syscfg.h | 62 +++++
tests/qtest/meson.build | 3 +-
tests/qtest/stm32l4xx_syscfg-test.c | 408 ++++++++++++++++++++++++++++
10 files changed, 778 insertions(+), 9 deletions(-)
create mode 100644 hw/misc/stm32l4xx_syscfg.c
create mode 100644 include/hw/misc/stm32l4xx_syscfg.h
create mode 100644 tests/qtest/stm32l4xx_syscfg-test.c
--
2.38.5
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH qemu 1/3] hw/misc: Implement STM32L4xx SYSCFG
2023-12-10 17:51 ` [PATCH qemu 1/3] hw/misc: Implement STM32L4xx SYSCFG ~inesvarhol
@ 2023-12-18 3:52 ` Alistair Francis
0 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2023-12-18 3:52 UTC (permalink / raw)
To: ~inesvarhol
Cc: qemu-devel, qemu-arm, alistair, philmd, peter.maydell,
ines.varhol, arnaud.minier
On Mon, Dec 11, 2023 at 5:06 AM ~inesvarhol <inesvarhol@git.sr.ht> wrote:
>
> From: Inès Varhol <ines.varhol@telecom-paris.fr>
>
> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
> ---
> hw/misc/Kconfig | 3 +
> hw/misc/meson.build | 1 +
> hw/misc/stm32l4xx_syscfg.c | 277 +++++++++++++++++++++++++++++
> hw/misc/trace-events | 6 +
> include/hw/misc/stm32l4xx_syscfg.h | 62 +++++++
> 5 files changed, 349 insertions(+)
> create mode 100644 hw/misc/stm32l4xx_syscfg.c
> create mode 100644 include/hw/misc/stm32l4xx_syscfg.h
>
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 3efe3dc2cc..a20427a9be 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -90,6 +90,9 @@ config STM32F4XX_EXTI
> config STM32L4X5_EXTI
> bool
>
> +config STM32L4XX_SYSCFG
> + bool
> +
> config MIPS_ITU
> bool
>
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 16db6e228d..120c59d9f4 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -111,6 +111,7 @@ system_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.
> system_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c'))
> system_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c'))
> system_ss.add(when: 'CONFIG_STM32L4X5_EXTI', if_true: files('stm32l4x5_exti.c'))
> +system_ss.add(when: 'CONFIG_STM32L4XX_SYSCFG', if_true: files('stm32l4xx_syscfg.c'))
> system_ss.add(when: 'CONFIG_MPS2_FPGAIO', if_true: files('mps2-fpgaio.c'))
> system_ss.add(when: 'CONFIG_MPS2_SCC', if_true: files('mps2-scc.c'))
>
> diff --git a/hw/misc/stm32l4xx_syscfg.c b/hw/misc/stm32l4xx_syscfg.c
> new file mode 100644
> index 0000000000..a8ef370117
> --- /dev/null
> +++ b/hw/misc/stm32l4xx_syscfg.c
> @@ -0,0 +1,277 @@
> +/*
> + * STM32L4xx SYSCFG (System Configuration Controller)
> + *
> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
> + * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
> + * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + *
> + * Based on the stm32f4xx_syscfg by Alistair Francis.
> + * The reference used is the STMicroElectronics RM0351 Reference manual
> + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
> + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "trace.h"
> +#include "hw/irq.h"
> +#include "migration/vmstate.h"
> +#include "hw/misc/stm32l4xx_syscfg.h"
> +
> +#define NUM_GPIOS 7
> +
> +#define SYSCFG_MEMRMP 0x00
> +#define SYSCFG_CFGR1 0x04
> +#define SYSCFG_EXTICR1 0x08
> +#define SYSCFG_EXTICR2 0x0C
> +#define SYSCFG_EXTICR3 0x10
> +#define SYSCFG_EXTICR4 0x14
> +#define SYSCFG_SCSR 0x18
> +#define SYSCFG_CFGR2 0x1C
> +#define SYSCFG_SWPR 0x20
> +#define SYSCFG_SKR 0x24
> +#define SYSCFG_SWPR2 0x28
> +
> +/* 00000000_00000000_00000001_00000111 */
> +#define ACTIVABLE_BITS_MEMRP 0x00000107
> +
> +/* 11111100_11111111_00000001_00000000 */
> +#define ACTIVABLE_BITS_CFGR1 0xFCFF0100
> +/* 00000000_00000000_00000000_00000001 */
> +#define FIREWALL_DISABLE_CFGR1 0x00000001
> +
> +/* 00000000_00000000_00000000_00000001 */
> +#define ACTIVABLE_BITS_EXTICR 0x0000FFFF
This doesn't match the comment
> +
> +/* 00000000_00000000_00000000_00000011 */
> +/* #define ACTIVABLE_BITS_SCSR 0x00000003 */
> +
> +/* 00000000_00000000_00000000_00001111 */
> +#define ECC_LOCK_CFGR2 0x0000000F
> +/* 00000000_00000000_00000001_00000000 */
> +#define SRAM2_PARITY_ERROR_FLAG_CFGR2 0x00000100
> +
> +/* 00000000_00000000_00000000_11111111 */
> +#define ACTIVABLE_BITS_SKR 0x000000FF
> +
> +static void stm32l4xx_syscfg_hold_reset(Object *obj)
> +{
> + STM32L4xxSyscfgState *s = STM32L4XX_SYSCFG(obj);
> +
> + s->memrmp = 0x00000000;
> + s->cfgr1 = 0x7C000001;
> + s->exticr[0] = 0x00000000;
> + s->exticr[1] = 0x00000000;
> + s->exticr[2] = 0x00000000;
> + s->exticr[3] = 0x00000000;
> + s->scsr = 0x00000000;
> + s->cfgr2 = 0x00000000;
> + s->swpr = 0x00000000;
> + s->skr = 0x00000000;
> + s->swpr2 = 0x00000000;
> +}
> +
> +static void stm32l4xx_syscfg_set_irq(void *opaque, int irq, int level)
> +{
> + STM32L4xxSyscfgState *s = opaque;
> + uint8_t gpio = irq / 16;
> + g_assert(gpio < NUM_GPIOS);
> +
> + int line = irq % 16;
> + int exticr_reg = line / 4;
> + int startbit = (irq % 4) * 4;
> +
> + trace_stm32l4xx_syscfg_set_irq(gpio, irq % 16, level);
`irq % 16` is just `line`
Also it would probably be worth replacing the 16 with a macro.
Otherwise looks good
Alistair
> +
> + if (extract32(s->exticr[exticr_reg], startbit, 4) == gpio) {
> + trace_stm32l4xx_syscfg_pulse_exti(line);
> + qemu_set_irq(s->gpio_out[line], level);
> + }
> +}
> +
> +static uint64_t stm32l4xx_syscfg_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + STM32L4xxSyscfgState *s = opaque;
> +
> + trace_stm32l4xx_syscfg_read(addr);
> +
> + switch (addr) {
> + case SYSCFG_MEMRMP:
> + return s->memrmp;
> + case SYSCFG_CFGR1:
> + return s->cfgr1;
> + case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
> + return s->exticr[(addr - SYSCFG_EXTICR1) / 4];
> + case SYSCFG_SCSR:
> + return s->scsr;
> + case SYSCFG_CFGR2:
> + return s->cfgr2;
> + case SYSCFG_SWPR:
> + return s->swpr;
> + case SYSCFG_SKR:
> + return s->skr;
> + case SYSCFG_SWPR2:
> + return s->swpr2;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
> + return 0;
> + }
> +}
> +
> +static void stm32l4xx_syscfg_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + STM32L4xxSyscfgState *s = opaque;
> + uint32_t value = val64;
> +
> + trace_stm32l4xx_syscfg_write(value, addr);
> +
> + switch (addr) {
> + case SYSCFG_MEMRMP:
> + qemu_log_mask(LOG_UNIMP,
> + "%s: Changing the memory mapping isn't supported\n",
> + __func__);
> + s->memrmp = value & ACTIVABLE_BITS_MEMRP;
> + return;
> + case SYSCFG_CFGR1:
> + qemu_log_mask(LOG_UNIMP,
> + "%s: Functions in CFGRx aren't supported\n",
> + __func__);
> + /* bit 0 (firewall dis.) is cleared by software, set only by reset. */
> + s->cfgr1 = (s->cfgr1 & value & FIREWALL_DISABLE_CFGR1) |
> + (value & ACTIVABLE_BITS_CFGR1);
> + return;
> + case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
> + s->exticr[(addr - SYSCFG_EXTICR1) / 4] =
> + (value & ACTIVABLE_BITS_EXTICR);
> + return;
> + case SYSCFG_SCSR:
> + qemu_log_mask(LOG_UNIMP,
> + "%s: Erasing SRAM2 isn't supported\n",
> + __func__);
> + /*
> + * only non reserved bits are :
> + * bit 0 (write-protected by a passkey), bit 1 (meant to be read)
> + * so it serves no purpose yet to add :
> + * s->scsr = value & 0x3;
> + */
> + return;
> + case SYSCFG_CFGR2:
> + qemu_log_mask(LOG_UNIMP,
> + "%s: Functions in CFGRx aren't supported\n",
> + __func__);
> + /* bit 8 (SRAM2 PEF) is cleared by software by writing a '1'.*/
> + /* bits[3:0] (ECC Lock) are set by software, cleared only by reset.*/
> + s->cfgr2 = (s->cfgr2 | (value & ECC_LOCK_CFGR2)) &
> + ~(value & SRAM2_PARITY_ERROR_FLAG_CFGR2);
> + return;
> + case SYSCFG_SWPR:
> + qemu_log_mask(LOG_UNIMP,
> + "%s: Write protecting SRAM2 isn't supported\n",
> + __func__);
> + /* These bits are set by software and cleared only by reset.*/
> + s->swpr |= value;
> + return;
> + case SYSCFG_SKR:
> + qemu_log_mask(LOG_UNIMP,
> + "%s: Erasing SRAM2 isn't supported\n",
> + __func__);
> + s->skr = value & ACTIVABLE_BITS_SKR;
> + return;
> + case SYSCFG_SWPR2:
> + qemu_log_mask(LOG_UNIMP,
> + "%s: Write protecting SRAM2 isn't supported\n",
> + __func__);
> + /* These bits are set by software and cleared only by reset.*/
> + s->swpr2 |= value;
> + return;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
> + }
> +}
> +
> +static const MemoryRegionOps stm32l4xx_syscfg_ops = {
> + .read = stm32l4xx_syscfg_read,
> + .write = stm32l4xx_syscfg_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .impl.min_access_size = 4,
> + .impl.max_access_size = 4,
> + .impl.unaligned = false,
> + .valid.min_access_size = 4,
> + .valid.max_access_size = 4,
> + .valid.unaligned = false,
> +};
> +
> +static void stm32l4xx_syscfg_init(Object *obj)
> +{
> + STM32L4xxSyscfgState *s = STM32L4XX_SYSCFG(obj);
> +
> + memory_region_init_io(&s->mmio, obj, &stm32l4xx_syscfg_ops, s,
> + TYPE_STM32L4XX_SYSCFG, 0x400);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
> +
> + qdev_init_gpio_in(DEVICE(obj), stm32l4xx_syscfg_set_irq, 16 * NUM_GPIOS);
> + qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
> +}
> +
> +static const VMStateDescription vmstate_stm32l4xx_syscfg = {
> + .name = TYPE_STM32L4XX_SYSCFG,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(memrmp, STM32L4xxSyscfgState),
> + VMSTATE_UINT32(cfgr1, STM32L4xxSyscfgState),
> + VMSTATE_UINT32_ARRAY(exticr, STM32L4xxSyscfgState,
> + SYSCFG_NUM_EXTICR),
> + VMSTATE_UINT32(scsr, STM32L4xxSyscfgState),
> + VMSTATE_UINT32(cfgr2, STM32L4xxSyscfgState),
> + VMSTATE_UINT32(swpr, STM32L4xxSyscfgState),
> + VMSTATE_UINT32(skr, STM32L4xxSyscfgState),
> + VMSTATE_UINT32(swpr2, STM32L4xxSyscfgState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void stm32l4xx_syscfg_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
> +
> + dc->vmsd = &vmstate_stm32l4xx_syscfg;
> + rc->phases.hold = stm32l4xx_syscfg_hold_reset;
> +}
> +
> +static const TypeInfo stm32l4xx_syscfg_info[] = {
> + {
> + .name = TYPE_STM32L4XX_SYSCFG,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(STM32L4xxSyscfgState),
> + .instance_init = stm32l4xx_syscfg_init,
> + .class_init = stm32l4xx_syscfg_class_init,
> + }
> +};
> +
> +DEFINE_TYPES(stm32l4xx_syscfg_info)
> diff --git a/hw/misc/trace-events b/hw/misc/trace-events
> index 2f01c62c0e..756cb45bd6 100644
> --- a/hw/misc/trace-events
> +++ b/hw/misc/trace-events
> @@ -163,6 +163,12 @@ stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
> stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
> stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
>
> +# stm32l4xx_syscfg.c
> +stm32l4xx_syscfg_set_irq(int gpio, int line, int level) "irq from GPIO: %d, line: %d, level: %d"
> +stm32l4xx_syscfg_pulse_exti(int irq) "irq %d forwarded to EXTI"
> +stm32l4xx_syscfg_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
> +stm32l4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
> +
> # stm32l4x5_exti.c
> stm32l4x5_exti_set_irq(int irq, int level) "Set EXTI: %d to %d"
> stm32l4x5_exti_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
> diff --git a/include/hw/misc/stm32l4xx_syscfg.h b/include/hw/misc/stm32l4xx_syscfg.h
> new file mode 100644
> index 0000000000..d9ed4da74e
> --- /dev/null
> +++ b/include/hw/misc/stm32l4xx_syscfg.h
> @@ -0,0 +1,62 @@
> +/*
> + * STM32L4xx SYSCFG (System Configuration Controller)
> + *
> + * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
> + * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
> + * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + *
> + * Based on the stm32f4xx_syscfg by Alistair Francis.
> + * The reference used is the STMicroElectronics RM0351 Reference manual
> + * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
> + * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
> + */
> +
> +#ifndef HW_STM32L4XX_SYSCFG_H
> +#define HW_STM32L4XX_SYSCFG_H
> +
> +#include "hw/sysbus.h"
> +#include "qom/object.h"
> +
> +#define TYPE_STM32L4XX_SYSCFG "stm32l4xx-syscfg"
> +OBJECT_DECLARE_SIMPLE_TYPE(STM32L4xxSyscfgState, STM32L4XX_SYSCFG)
> +
> +#define SYSCFG_NUM_EXTICR 4
> +
> +struct STM32L4xxSyscfgState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> +
> + uint32_t memrmp;
> + uint32_t cfgr1;
> + uint32_t exticr[SYSCFG_NUM_EXTICR];
> + uint32_t scsr;
> + uint32_t cfgr2;
> + uint32_t swpr;
> + uint32_t skr;
> + uint32_t swpr2;
> +
> + qemu_irq gpio_out[16];
> +};
> +
> +#endif
> --
> 2.38.5
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH qemu 2/3] tests/qtest: Add STM32L4xx SYSCFG QTest testcase
2023-12-10 17:55 ` [PATCH qemu 2/3] tests/qtest: Add STM32L4xx SYSCFG QTest testcase ~inesvarhol
@ 2023-12-18 3:53 ` Alistair Francis
0 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2023-12-18 3:53 UTC (permalink / raw)
To: ~inesvarhol
Cc: qemu-devel, qemu-arm, alistair, philmd, peter.maydell,
ines.varhol, arnaud.minier
On Mon, Dec 11, 2023 at 5:07 AM ~inesvarhol <inesvarhol@git.sr.ht> wrote:
>
> From: Inès Varhol <ines.varhol@telecom-paris.fr>
>
> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/qtest/meson.build | 3 +-
> tests/qtest/stm32l4xx_syscfg-test.c | 408 ++++++++++++++++++++++++++++
> 2 files changed, 410 insertions(+), 1 deletion(-)
> create mode 100644 tests/qtest/stm32l4xx_syscfg-test.c
>
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index d5126f4d86..06a04ed17d 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -196,7 +196,8 @@ qtests_aspeed = \
> 'aspeed_gpio-test']
>
> qtests_stm32l4x5 = \
> - ['stm32l4x5_exti-test']
> + ['stm32l4x5_exti-test',
> + 'stm32l4xx_syscfg-test']
>
> qtests_arm = \
> (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
> diff --git a/tests/qtest/stm32l4xx_syscfg-test.c b/tests/qtest/stm32l4xx_syscfg-test.c
> new file mode 100644
> index 0000000000..166b596ba6
> --- /dev/null
> +++ b/tests/qtest/stm32l4xx_syscfg-test.c
> @@ -0,0 +1,408 @@
> +/*
> + * QTest testcase for STM32L4xx_SYSCFG
> + *
> + * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
> + * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "libqtest-single.h"
> +
> +#define SYSCFG_BASE_ADDR 0x40010000
> +#define SYSCFG_MEMRMP 0x00
> +#define SYSCFG_CFGR1 0x04
> +#define SYSCFG_EXTICR1 0x08
> +#define SYSCFG_EXTICR2 0x0C
> +#define SYSCFG_EXTICR3 0x10
> +#define SYSCFG_EXTICR4 0x14
> +#define SYSCFG_SCSR 0x18
> +#define SYSCFG_CFGR2 0x1C
> +#define SYSCFG_SWPR 0x20
> +#define SYSCFG_SKR 0x24
> +#define SYSCFG_SWPR2 0x28
> +#define INVALID_ADDR 0x2C
> +
> +#define EXTI_BASE_ADDR 0x40010400
> +#define EXTI_IMR1 0x00
> +#define EXTI_RTSR1 0x08
> +#define EXTI_FTSR1 0x0C
> +
> +static void syscfg_writel(unsigned int offset, uint32_t value)
> +{
> + writel(SYSCFG_BASE_ADDR + offset, value);
> +}
> +
> +static uint32_t syscfg_readl(unsigned int offset)
> +{
> + return readl(SYSCFG_BASE_ADDR + offset);
> +}
> +
> +static void exti_writel(unsigned int offset, uint32_t value)
> +{
> + writel(EXTI_BASE_ADDR + offset, value);
> +}
> +
> +static void system_reset(void)
> +{
> + QDict *response;
> + response = qtest_qmp(global_qtest, "{'execute': 'system_reset'}");
> + g_assert(qdict_haskey(response, "return"));
> + qobject_unref(response);
> +}
> +
> +static void test_reset(void)
> +{
> + /*
> + * Test that registers are initialized at the correct values
> + */
> + const uint32_t memrmp = syscfg_readl(SYSCFG_MEMRMP);
> + g_assert_cmpuint(memrmp, ==, 0x00000000);
> +
> + const uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
> + g_assert_cmpuint(cfgr1, ==, 0x7C000001);
> +
> + const uint32_t exticr1 = syscfg_readl(SYSCFG_EXTICR1);
> + g_assert_cmpuint(exticr1, ==, 0x00000000);
> +
> + const uint32_t exticr2 = syscfg_readl(SYSCFG_EXTICR2);
> + g_assert_cmpuint(exticr2, ==, 0x00000000);
> +
> + const uint32_t exticr3 = syscfg_readl(SYSCFG_EXTICR3);
> + g_assert_cmpuint(exticr3, ==, 0x00000000);
> +
> + const uint32_t exticr4 = syscfg_readl(SYSCFG_EXTICR4);
> + g_assert_cmpuint(exticr4, ==, 0x00000000);
> +
> + const uint32_t scsr = syscfg_readl(SYSCFG_SCSR);
> + g_assert_cmpuint(scsr, ==, 0x00000000);
> +
> + const uint32_t cfgr2 = syscfg_readl(SYSCFG_CFGR2);
> + g_assert_cmpuint(cfgr2, ==, 0x00000000);
> +
> + const uint32_t swpr = syscfg_readl(SYSCFG_SWPR);
> + g_assert_cmpuint(swpr, ==, 0x00000000);
> +
> + const uint32_t skr = syscfg_readl(SYSCFG_SKR);
> + g_assert_cmpuint(skr, ==, 0x00000000);
> +
> + const uint32_t swpr2 = syscfg_readl(SYSCFG_SWPR2);
> + g_assert_cmpuint(swpr2, ==, 0x00000000);
> +}
> +
> +static void test_reserved_bits(void)
> +{
> + /*
> + * Test that reserved bits stay at reset value
> + * (which is 0 for all of them) by writing '1'
> + * in all reserved bits (keeping reset value for
> + * other bits) and checking that the
> + * register is still at reset value
> + */
> + syscfg_writel(SYSCFG_MEMRMP, 0xFFFFFEF8);
> + const uint32_t memrmp = syscfg_readl(SYSCFG_MEMRMP);
> + g_assert_cmpuint(memrmp, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_CFGR1, 0x7F00FEFF);
> + const uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
> + g_assert_cmpuint(cfgr1, ==, 0x7C000001);
> +
> + syscfg_writel(SYSCFG_EXTICR1, 0xFFFF0000);
> + const uint32_t exticr1 = syscfg_readl(SYSCFG_EXTICR1);
> + g_assert_cmpuint(exticr1, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_EXTICR2, 0xFFFF0000);
> + const uint32_t exticr2 = syscfg_readl(SYSCFG_EXTICR2);
> + g_assert_cmpuint(exticr2, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_EXTICR3, 0xFFFF0000);
> + const uint32_t exticr3 = syscfg_readl(SYSCFG_EXTICR3);
> + g_assert_cmpuint(exticr3, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_EXTICR4, 0xFFFF0000);
> + const uint32_t exticr4 = syscfg_readl(SYSCFG_EXTICR4);
> + g_assert_cmpuint(exticr4, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_SKR, 0xFFFFFF00);
> + const uint32_t skr = syscfg_readl(SYSCFG_SKR);
> + g_assert_cmpuint(skr, ==, 0x00000000);
> +}
> +
> +static void test_set_and_clear(void)
> +{
> + /*
> + * Test that regular bits can be set and cleared
> + */
> + syscfg_writel(SYSCFG_MEMRMP, 0x00000107);
> + uint32_t memrmp = syscfg_readl(SYSCFG_MEMRMP);
> + g_assert_cmpuint(memrmp, ==, 0x00000107);
> + syscfg_writel(SYSCFG_MEMRMP, 0x00000000);
> + memrmp = syscfg_readl(SYSCFG_MEMRMP);
> + g_assert_cmpuint(memrmp, ==, 0x00000000);
> +
> + /* cfgr1 bit 0 is clear only so we keep it set */
> + syscfg_writel(SYSCFG_CFGR1, 0xFCFF0101);
> + uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
> + g_assert_cmpuint(cfgr1, ==, 0xFCFF0101);
> + syscfg_writel(SYSCFG_CFGR1, 0x00000001);
> + cfgr1 = syscfg_readl(SYSCFG_CFGR1);
> + g_assert_cmpuint(cfgr1, ==, 0x00000001);
> +
> + syscfg_writel(SYSCFG_EXTICR1, 0x0000FFFF);
> + uint32_t exticr1 = syscfg_readl(SYSCFG_EXTICR1);
> + g_assert_cmpuint(exticr1, ==, 0x0000FFFF);
> + syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
> + exticr1 = syscfg_readl(SYSCFG_EXTICR1);
> + g_assert_cmpuint(exticr1, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_EXTICR2, 0x0000FFFF);
> + uint32_t exticr2 = syscfg_readl(SYSCFG_EXTICR2);
> + g_assert_cmpuint(exticr2, ==, 0x0000FFFF);
> + syscfg_writel(SYSCFG_EXTICR2, 0x00000000);
> + exticr2 = syscfg_readl(SYSCFG_EXTICR2);
> + g_assert_cmpuint(exticr2, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_EXTICR3, 0x0000FFFF);
> + uint32_t exticr3 = syscfg_readl(SYSCFG_EXTICR3);
> + g_assert_cmpuint(exticr3, ==, 0x0000FFFF);
> + syscfg_writel(SYSCFG_EXTICR3, 0x00000000);
> + exticr3 = syscfg_readl(SYSCFG_EXTICR3);
> + g_assert_cmpuint(exticr3, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_EXTICR4, 0x0000FFFF);
> + uint32_t exticr4 = syscfg_readl(SYSCFG_EXTICR4);
> + g_assert_cmpuint(exticr4, ==, 0x0000FFFF);
> + syscfg_writel(SYSCFG_EXTICR4, 0x00000000);
> + exticr4 = syscfg_readl(SYSCFG_EXTICR4);
> + g_assert_cmpuint(exticr4, ==, 0x00000000);
> +
> + syscfg_writel(SYSCFG_SKR, 0x000000FF);
> + uint32_t skr = syscfg_readl(SYSCFG_SKR);
> + g_assert_cmpuint(skr, ==, 0x000000FF);
> + syscfg_writel(SYSCFG_SKR, 0x00000000);
> + skr = syscfg_readl(SYSCFG_SKR);
> + g_assert_cmpuint(skr, ==, 0x00000000);
> +}
> +
> +static void test_clear_by_writing_1(void)
> +{
> + /*
> + * Test that writing '1' doesn't set the bit
> + */
> + syscfg_writel(SYSCFG_CFGR2, 0x00000100);
> + const uint32_t cfgr2 = syscfg_readl(SYSCFG_CFGR2);
> + g_assert_cmpuint(cfgr2, ==, 0x00000000);
> +}
> +
> +static void test_set_only_bits(void)
> +{
> + /*
> + * Test that set only bits stay can't be cleared
> + */
> + syscfg_writel(SYSCFG_CFGR2, 0x0000000F);
> + syscfg_writel(SYSCFG_CFGR2, 0x00000000);
> + const uint32_t exticr3 = syscfg_readl(SYSCFG_CFGR2);
> + g_assert_cmpuint(exticr3, ==, 0x0000000F);
> +
> + syscfg_writel(SYSCFG_SWPR, 0xFFFFFFFF);
> + syscfg_writel(SYSCFG_SWPR, 0x00000000);
> + const uint32_t swpr = syscfg_readl(SYSCFG_SWPR);
> + g_assert_cmpuint(swpr, ==, 0xFFFFFFFF);
> +
> + syscfg_writel(SYSCFG_SWPR2, 0xFFFFFFFF);
> + syscfg_writel(SYSCFG_SWPR2, 0x00000000);
> + const uint32_t swpr2 = syscfg_readl(SYSCFG_SWPR2);
> + g_assert_cmpuint(swpr2, ==, 0xFFFFFFFF);
> +
> + system_reset();
> +}
> +
> +static void test_clear_only_bits(void)
> +{
> + /*
> + * Test that clear only bits stay can't be set
> + */
> + syscfg_writel(SYSCFG_CFGR1, 0x00000000);
> + syscfg_writel(SYSCFG_CFGR1, 0x00000001);
> + const uint32_t cfgr1 = syscfg_readl(SYSCFG_CFGR1);
> + g_assert_cmpuint(cfgr1, ==, 0x00000000);
> +
> + system_reset();
> +}
> +
> +static void test_interrupt(void)
> +{
> + /*
> + * Test that GPIO rising lines result in an irq
> + * with the right configuration
> + */
> + qtest_irq_intercept_in(global_qtest, "/machine/unattached/device[0]/exti");
> + /* Enable interrupt on rising edge of GPIO PA[0] */
> + exti_writel(EXTI_IMR1, 0x00000001);
> + exti_writel(EXTI_RTSR1, 0x00000001);
> +
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 1);
> +
> + g_assert_true(get_irq(0));
> +
> + /* Enable interrupt on rising edge of GPIO PA[15] */
> + exti_writel(EXTI_IMR1, 0x00008000);
> + exti_writel(EXTI_RTSR1, 0x00008000);
> +
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 15, 1);
> +
> + g_assert_true(get_irq(15));
> +
> + /* Enable interrupt on rising edge of GPIO PB[1] */
> + syscfg_writel(SYSCFG_EXTICR1, 0x00000010);
> + exti_writel(EXTI_IMR1, 0x00000002);
> + exti_writel(EXTI_RTSR1, 0x00000002);
> +
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 17, 1);
> +
> + g_assert_true(get_irq(1));
> +
> + /* Clean the test */
> + syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 0);
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 15, 0);
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 17, 0);
> +}
> +
> +static void test_irq_pin_multiplexer(void)
> +{
> + /*
> + * Test that syscfg irq sets the right exti irq
> + */
> +
> + qtest_irq_intercept_in(global_qtest, "/machine/unattached/device[0]/exti");
> +
> + /* Enable interrupt on rising edge of GPIO PA[0] */
> + exti_writel(EXTI_IMR1, 0x00000001);
> + exti_writel(EXTI_RTSR1, 0x00000001);
> +
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 1);
> +
> + /* Check that irq 0 was set and irq 15 wasn't */
> + g_assert_true(get_irq(0));
> + g_assert_false(get_irq(15));
> +
> + /* Clean the test */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 0);
> +
> + /* Enable interrupt on rising edge of GPIO PA[15] */
> + exti_writel(EXTI_IMR1, 0x00008000);
> + exti_writel(EXTI_RTSR1, 0x00008000);
> +
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 15, 1);
> +
> + /* Check that irq 15 was set and irq 0 wasn't */
> + g_assert_true(get_irq(15));
> + g_assert_false(get_irq(0));
> +
> + /* Clean the test */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 15, 0);
> +}
> +
> +static void test_irq_gpio_multiplexer(void)
> +{
> + /*
> + * Test that an irq is generated only by the right GPIO
> + */
> +
> + qtest_irq_intercept_in(global_qtest, "/machine/unattached/device[0]/exti");
> +
> + /* Enable interrupt on rising edge of GPIO PA[0] */
> + exti_writel(EXTI_IMR1, 0x00000001);
> + exti_writel(EXTI_RTSR1, 0x00000001);
> +
> + /* Check that setting rising pin GPIOA[0] generates an irq */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 1);
> +
> + g_assert_true(get_irq(0));
> +
> + /* Clean the test */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 0);
> +
> + /* Check that setting rising pin GPIOB[0] doesn't generate an irq */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 16, 1);
> +
> + g_assert_false(get_irq(0));
> +
> + /* Clean the test */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 16, 0);
> +
> + /* Enable interrupt on rising edge of GPIO PB[0] */
> + exti_writel(EXTI_IMR1, 0x00000001);
> + exti_writel(EXTI_RTSR1, 0x00000001);
> + syscfg_writel(SYSCFG_EXTICR1, 0x00000001);
> +
> + /* Check that setting rising pin GPIOA[0] doesn't generate an irq */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 1);
> +
> + g_assert_false(get_irq(0));
> +
> + /* Clean the test */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 0, 0);
> +
> + /* Check that setting rising pin GPIOB[0] generates an irq */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 16, 1);
> +
> + g_assert_true(get_irq(0));
> +
> + /* Clean the test */
> + qtest_set_irq_in(global_qtest, "/machine/unattached/device[0]/syscfg",
> + NULL, 16, 0);
> + syscfg_writel(SYSCFG_EXTICR1, 0x00000000);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + int ret;
> +
> + g_test_init(&argc, &argv, NULL);
> + g_test_set_nonfatal_assertions();
> +
> + qtest_add_func("stm32l4x5/syscfg/test_reset", test_reset);
> + qtest_add_func("stm32l4x5/syscfg/test_reserved_bits",
> + test_reserved_bits);
> + qtest_add_func("stm32l4x5/syscfg/test_set_and_clear",
> + test_set_and_clear);
> + qtest_add_func("stm32l4x5/syscfg/test_clear_by_writing_1",
> + test_clear_by_writing_1);
> + qtest_add_func("stm32l4x5/syscfg/test_set_only_bits",
> + test_set_only_bits);
> + qtest_add_func("stm32l4x5/syscfg/test_clear_only_bits",
> + test_clear_only_bits);
> + qtest_add_func("stm32l4x5/syscfg/test_interrupt",
> + test_interrupt);
> + qtest_add_func("stm32l4x5/syscfg/test_irq_pin_multiplexer",
> + test_irq_pin_multiplexer);
> + qtest_add_func("stm32l4x5/syscfg/test_irq_gpio_multiplexer",
> + test_irq_gpio_multiplexer);
> +
> + qtest_start("-machine b-l475e-iot01a");
> + ret = g_test_run();
> + qtest_end();
> +
> + return ret;
> +}
> --
> 2.38.5
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH qemu 3/3] hw/arm: Connect STM32L4xx SYSCFG to STM32L4x5 SoC
2023-12-10 18:06 ` [PATCH qemu 3/3] hw/arm: Connect STM32L4xx SYSCFG to STM32L4x5 SoC ~inesvarhol
@ 2023-12-18 3:57 ` Alistair Francis
0 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2023-12-18 3:57 UTC (permalink / raw)
To: ~inesvarhol
Cc: qemu-devel, qemu-arm, alistair, philmd, peter.maydell,
ines.varhol, arnaud.minier
On Mon, Dec 11, 2023 at 5:06 AM ~inesvarhol <inesvarhol@git.sr.ht> wrote:
>
> From: Inès Varhol <ines.varhol@telecom-paris.fr>
>
> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
> ---
> hw/arm/Kconfig | 1 +
> hw/arm/stm32l4x5_soc.c | 24 ++++++++++++++++--------
> include/hw/arm/stm32l4x5_soc.h | 2 ++
> 3 files changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 9c9d5bb541..ea77977d4b 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -458,6 +458,7 @@ config STM32L4X5_SOC
> bool
> select ARM_V7M
> select OR_IRQ
> + select STM32L4XX_SYSCFG
> select STM32L4X5_EXTI
>
> config XLNX_ZYNQMP_ARM
> diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c
> index cf786eac1d..9b45a9e606 100644
> --- a/hw/arm/stm32l4x5_soc.c
> +++ b/hw/arm/stm32l4x5_soc.c
> @@ -46,6 +46,7 @@
> #define SRAM2_SIZE (32 * KiB)
>
> #define EXTI_ADDR 0x40010400
> +#define SYSCFG_ADDR 0x40010000
>
> #define NUM_EXTI_IRQ 40
> /* Match exti line connections with their CPU IRQ number */
> @@ -90,6 +91,8 @@ static void stm32l4x5_soc_initfn(Object *obj)
>
> object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI);
>
> + object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4XX_SYSCFG);
> +
> s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
> }
> @@ -167,6 +170,15 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> return;
> }
>
> + /* System configuration controller */
> + dev = DEVICE(&s->syscfg);
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, SYSCFG_ADDR);
What about the SYSCFG in GPIOs?
You don't have to connect them now, but it would be worth mentioning
in the commit message that they aren't connected and why
Alistair
> +
> + /* EXTI device */
> dev = DEVICE(&s->exti);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) {
> return;
> @@ -178,13 +190,10 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
> }
>
> - /*
> - * Uncomment when Syscfg is implemented
> - * for (i = 0; i < 16; i++) {
> - * qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
> - * qdev_get_gpio_in(dev, i));
> - * }
> - */
> + for (i = 0; i < 16; i++) {
> + qdev_connect_gpio_out(DEVICE(&s->syscfg), i,
> + qdev_get_gpio_in(dev, i));
> + }
>
> /* APB1 BUS */
> create_unimplemented_device("TIM2", 0x40000000, 0x400);
> @@ -223,7 +232,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp)
> /* RESERVED: 0x40009800, 0x6800 */
>
> /* APB2 BUS */
> - create_unimplemented_device("SYSCFG", 0x40010000, 0x30);
> create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0);
> create_unimplemented_device("COMP", 0x40010200, 0x200);
> /* RESERVED: 0x40010800, 0x1400 */
> diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h
> index ac47158596..5ff757f15b 100644
> --- a/include/hw/arm/stm32l4x5_soc.h
> +++ b/include/hw/arm/stm32l4x5_soc.h
> @@ -37,6 +37,7 @@
> #include "qemu/units.h"
> #include "hw/qdev-core.h"
> #include "hw/arm/armv7m.h"
> +#include "hw/misc/stm32l4xx_syscfg.h"
> #include "hw/misc/stm32l4x5_exti.h"
> #include "qom/object.h"
>
> @@ -52,6 +53,7 @@ struct Stm32l4x5SocState {
> ARMv7MState armv7m;
>
> Stm32l4x5ExtiState exti;
> + STM32L4xxSyscfgState syscfg;
>
> MemoryRegion sram1;
> MemoryRegion sram2;
> --
> 2.38.5
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-12-18 3:58 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-12-10 19:05 [PATCH qemu 0/3] [PATCH qemu 0/3] hw/arm: Add device STM32L4x5 SYSCFG ~inesvarhol
2023-12-10 17:51 ` [PATCH qemu 1/3] hw/misc: Implement STM32L4xx SYSCFG ~inesvarhol
2023-12-18 3:52 ` Alistair Francis
2023-12-10 17:55 ` [PATCH qemu 2/3] tests/qtest: Add STM32L4xx SYSCFG QTest testcase ~inesvarhol
2023-12-18 3:53 ` Alistair Francis
2023-12-10 18:06 ` [PATCH qemu 3/3] hw/arm: Connect STM32L4xx SYSCFG to STM32L4x5 SoC ~inesvarhol
2023-12-18 3:57 ` Alistair Francis
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