Re: [PATCH v11 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk

[Alistair Francis <alistair23@gmail.com>]

On Thu, Aug 29, 2024 at 3:53 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> sspush and sspopchk have equivalent compressed encoding taken from zcmop.
> cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding
> for both rs1 and rs2 from space bitfield, this required a new codec.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  disas/riscv.c | 19 ++++++++++++++++++-
>  disas/riscv.h |  1 +
>  2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 5eafb7f7f3..6e9ba42edd 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -980,6 +980,8 @@ typedef enum {
>      rv_op_ssrdp = 949,
>      rv_op_ssamoswap_w = 950,
>      rv_op_ssamoswap_d = 951,
> +    rv_op_c_sspush = 952,
> +    rv_op_c_sspopchk = 953,
>  } rv_op;
>
>  /* register names */
> @@ -2244,6 +2246,10 @@ const rv_opcode_data rvi_opcode_data[] = {
>      { "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 },
>      { "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
>      { "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
> +    { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
> +      rv_op_sspush, 0 },
> +    { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
> +      rv_op_sspopchk, 0 },
>  };
>
>  /* CSR names */
> @@ -2604,7 +2610,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
>              if (dec->cfg->ext_zcmop) {
>                  if ((((inst >> 2) & 0b111111) == 0b100000) &&
>                      (((inst >> 11) & 0b11) == 0b0)) {
> -                    op = rv_c_mop_1 + ((inst >> 8) & 0b111);
> +                    unsigned int cmop_code = 0;
> +                    cmop_code = ((inst >> 8) & 0b111);
> +                    op = rv_c_mop_1 + cmop_code;
> +                    if (dec->cfg->ext_zicfiss) {
> +                        op = (cmop_code == 0) ? rv_op_c_sspush : op;
> +                        op = (cmop_code == 2) ? rv_op_c_sspopchk : op;
> +                    }
>                      break;
>                  }
>              }
> @@ -4923,6 +4935,11 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
>      case rv_codec_lp:
>          dec->imm = operand_lpl(inst);
>          break;
> +    case rv_codec_cmop_ss:
> +        dec->rd = rv_ireg_zero;
> +        dec->rs1 = dec->rs2 = operand_crs1(inst);
> +        dec->imm = 0;
> +        break;
>      };
>  }
>
> diff --git a/disas/riscv.h b/disas/riscv.h
> index 4895c5a301..6a3b371cd3 100644
> --- a/disas/riscv.h
> +++ b/disas/riscv.h
> @@ -167,6 +167,7 @@ typedef enum {
>      rv_codec_r2_imm2_imm5,
>      rv_codec_fli,
>      rv_codec_lp,
> +    rv_codec_cmop_ss,
>  } rv_codec;
>
>  /* structures */
> --
> 2.44.0
>
>