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To: Tommy Wu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, frank.chang@sifive.com, alistair.francis@wdc.com, apatel@ventanamicro.com, palmer@rivosinc.com, dbarboza@ventanamicro.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=alistair23@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, May 23, 2023 at 9:46=E2=80=AFPM Tommy Wu wrot= e: > > When we change the cpu extension state after the cpu is > realized, we cannot print the value of some CSRs in the remote > gdb debugger. The root cause is that the dynamic CSR xml is > generated when the cpu is realized. > > This patch add a function to refresh the dynamic CSR xml after > the cpu is realized. > > Signed-off-by: Tommy Wu > Reviewed-by: Frank Chang > --- > target/riscv/cpu.h | 2 ++ > target/riscv/gdbstub.c | 12 ++++++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index de7e43126a..dc8e592275 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -494,6 +494,7 @@ struct ArchCPU { > CPUNegativeOffsetState neg; > CPURISCVState env; > > + int dyn_csr_base_reg; > char *dyn_csr_xml; > char *dyn_vreg_xml; > > @@ -781,6 +782,7 @@ void riscv_get_csr_ops(int csrno, riscv_csr_operation= s *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > +void riscv_refresh_dynamic_csr_xml(CPUState *cs); > > uint8_t satp_mode_max_from_map(uint32_t map); > const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index 524bede865..9e97ee2c35 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -230,6 +230,8 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, in= t base_reg) > bitsize =3D 64; > } > > + cpu->dyn_csr_base_reg =3D base_reg; > + > g_string_printf(s, ""); > g_string_append_printf(s, ""); > g_string_append_printf(s, ""); > @@ -349,3 +351,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUSta= te *cs) > "riscv-csr.xml", 0); > } > } > + > +void riscv_refresh_dynamic_csr_xml(CPUState *cs) > +{ > + RISCVCPU *cpu =3D RISCV_CPU(cs); > + if (!cpu->dyn_csr_xml) { > + g_assert_not_reached(); > + } > + g_free(cpu->dyn_csr_xml); > + riscv_gen_dynamic_csr_xml(cs, cpu->dyn_csr_base_reg); I don't really understand why we need dyn_csr_base_reg, could we just use cs->gdb_num_regs directly here? Alistair > +} > -- > 2.38.1 > >