From: Alistair Francis <alistair23@gmail.com>
To: Michael Clark <mjc@sifive.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
palmer@sifive.com,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
patches@groups.riscv.org
Subject: Re: [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags
Date: Thu, 03 May 2018 21:22:37 +0000 [thread overview]
Message-ID: <CAKmqyKOgHg0Con2G1078R81P_gQk5ZrdDiGfry8Fc0sETW27mw@mail.gmail.com> (raw)
In-Reply-To: <1524699938-6764-31-git-send-email-mjc@sifive.com>
On Wed, Apr 25, 2018 at 5:00 PM Michael Clark <mjc@sifive.com> wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
Did Richard's SOB line get dropped?
Alistair
> ---
> target/riscv/cpu.h | 6 +++---
> target/riscv/translate.c | 10 +++++-----
> 2 files changed, 8 insertions(+), 8 deletions(-)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3fed92d..6fb0014 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -270,8 +270,8 @@ void QEMU_NORETURN
do_raise_exception_err(CPURISCVState *env,
> target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
> -#define TB_FLAGS_MMU_MASK 3
> -#define TB_FLAGS_FP_ENABLE MSTATUS_FS
> +#define TB_FLAGS_MMU_MASK 3
> +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
> target_ulong *cs_base, uint32_t
*flags)
> @@ -279,7 +279,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
*env, target_ulong *pc,
> *pc = env->pc;
> *cs_base = 0;
> #ifdef CONFIG_USER_ONLY
> - *flags = TB_FLAGS_FP_ENABLE;
> + *flags = TB_FLAGS_MSTATUS_FS;
> #else
> *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
> #endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index c0e6a04..4180c42 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -43,7 +43,7 @@ typedef struct DisasContext {
> target_ulong pc;
> target_ulong next_pc;
> uint32_t opcode;
> - uint32_t flags;
> + uint32_t mstatus_fs;
> uint32_t mem_idx;
> int singlestep_enabled;
> int bstate;
> @@ -664,7 +664,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t
opc, int rd,
> {
> TCGv t0;
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> + if (ctx->mstatus_fs == 0) {
> gen_exception_illegal(ctx);
> return;
> }
> @@ -694,7 +694,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t
opc, int rs1,
> {
> TCGv t0;
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> + if (ctx->mstatus_fs == 0) {
> gen_exception_illegal(ctx);
> return;
> }
> @@ -985,7 +985,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t
opc, int rd,
> {
> TCGv t0 = NULL;
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> + if (ctx->mstatus_fs == 0) {
> goto do_illegal;
> }
> @@ -1863,8 +1863,8 @@ void gen_intermediate_code(CPUState *cs,
TranslationBlock *tb)
> ctx.tb = tb;
> ctx.bstate = BS_NONE;
> - ctx.flags = tb->flags;
> ctx.mem_idx = tb->flags & TB_FLAGS_MMU_MASK;
> + ctx.mstatus_fs = tb->flags & TB_FLAGS_MSTATUS_FS;
> ctx.frm = -1; /* unknown rounding mode */
> num_insns = 0;
> --
> 2.7.0
next prev parent reply other threads:[~2018-05-03 21:23 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-25 23:45 [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 01/35] RISC-V: Replace hardcoded constants with enum values Michael Clark
2018-04-26 16:37 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 02/35] RISC-V: Make virt board description match spike Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 03/35] RISC-V: Use ROM base address and size from memmap Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 04/35] RISC-V: Remove identity_translate from load_elf Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 05/35] RISC-V: Remove unused class definitions Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly Michael Clark
2018-04-26 17:05 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 07/35] RISC-V: Make some header guards more specific Michael Clark
2018-04-26 16:43 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 08/35] RISC-V: Make virt header comment title consistent Michael Clark
2018-04-26 16:42 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection Michael Clark
2018-04-26 16:42 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c Michael Clark
2018-04-25 23:51 ` [Qemu-devel] [patches] " Palmer Dabbelt
2018-04-26 16:48 ` [Qemu-devel] " Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code Michael Clark
2018-04-26 16:48 ` Alistair Francis
2018-04-27 5:22 ` Michael Clark
2018-04-27 5:34 ` Michael Clark
2018-04-27 16:17 ` Alistair Francis
2018-05-04 1:45 ` Michael Clark
2018-05-04 23:44 ` Alistair Francis
2018-05-04 23:54 ` Alistair Francis
2018-05-05 2:02 ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 12/35] RISC-V: Update address bits to support sv39 and sv48 Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 13/35] RISC-V: Improve page table walker spec compliance Michael Clark
2018-05-03 20:49 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 14/35] RISC-V: Update E order and I extension order Michael Clark
2018-04-26 17:11 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case Michael Clark
2018-04-26 17:21 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 16/35] RISC-V: Make mtvec/stvec ignore vectored traps Michael Clark
2018-04-26 17:27 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 17/35] RISC-V: No traps on writes to misa, minstret, mcycle Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 18/35] RISC-V: Clear mtval/stval on exceptions without info Michael Clark
2018-04-26 17:36 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 Michael Clark
2018-04-26 20:02 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 20/35] RISC-V: Use [ms]counteren CSRs " Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 21/35] RISC-V: Add mcycle/minstret support for -icount auto Michael Clark
2018-04-26 20:05 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 22/35] RISC-V: Use atomic_cmpxchg to update PLIC bitmaps Michael Clark
2018-04-27 0:14 ` Richard Henderson
2018-04-27 7:18 ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending Michael Clark
2018-04-27 22:33 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs Michael Clark
2018-05-03 20:54 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper Michael Clark
2018-04-26 17:42 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions Michael Clark
2018-05-03 20:56 ` Alistair Francis
2018-05-04 4:21 ` Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates Michael Clark
2018-05-03 21:11 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs Michael Clark
2018-05-03 21:21 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags Michael Clark
2018-05-03 21:22 ` Alistair Francis [this message]
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table Michael Clark
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 34/35] RISC-V: Add hartid and \n to interrupt logging Michael Clark
2018-05-03 21:25 ` Alistair Francis
2018-04-25 23:45 ` [Qemu-devel] [PATCH v8 35/35] RISC-V: Use riscv prefix consistently on cpu helpers Michael Clark
2018-04-26 1:42 ` [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates Michael Clark
2018-04-26 2:01 ` Michael Clark
2018-04-26 18:22 ` Alistair Francis
2018-04-27 0:34 ` Michael Clark
2018-04-27 10:19 ` Peter Maydell
2018-04-27 0:35 ` Richard Henderson
2018-04-27 5:00 ` Michael Clark
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