* [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
@ 2023-06-09 5:59 Tommy Wu
2023-06-12 3:01 ` Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Tommy Wu @ 2023-06-09 5:59 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Tommy Wu, Frank Chang, Alistair Francis, Anup Patel,
Mayuresh Chitale, Ivan Klokov
According to the `The RISC-V Advanced Interrupt Architecture`
document, if register `mmsiaddrcfgh` of the domain has bit L set
to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/intc/riscv_aplic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index afc5b54dbb..4bdc6a5d1a 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -688,13 +688,13 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
* domains).
*/
if (aplic->num_children &&
- !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
aplic->smsicfgaddr = value;
}
} else if (aplic->mmode && aplic->msimode &&
(addr == APLIC_SMSICFGADDRH)) {
if (aplic->num_children &&
- !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
+ !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
}
} else if ((APLIC_SETIP_BASE <= addr) &&
--
2.31.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
2023-06-09 5:59 [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Tommy Wu
@ 2023-06-12 3:01 ` Alistair Francis
2023-06-12 3:15 ` Anup Patel
2023-06-12 4:11 ` Alistair Francis
2 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2023-06-12 3:01 UTC (permalink / raw)
To: Tommy Wu
Cc: qemu-devel, qemu-riscv, Frank Chang, Alistair Francis, Anup Patel,
Mayuresh Chitale, Ivan Klokov
On Fri, Jun 9, 2023 at 4:01 PM Tommy Wu <tommy.wu@sifive.com> wrote:
>
> According to the `The RISC-V Advanced Interrupt Architecture`
> document, if register `mmsiaddrcfgh` of the domain has bit L set
> to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
> read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
>
> Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/riscv_aplic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index afc5b54dbb..4bdc6a5d1a 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -688,13 +688,13 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
> * domains).
> */
> if (aplic->num_children &&
> - !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> + !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> aplic->smsicfgaddr = value;
> }
> } else if (aplic->mmode && aplic->msimode &&
> (addr == APLIC_SMSICFGADDRH)) {
> if (aplic->num_children &&
> - !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> + !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
> }
> } else if ((APLIC_SETIP_BASE <= addr) &&
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
2023-06-09 5:59 [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Tommy Wu
2023-06-12 3:01 ` Alistair Francis
@ 2023-06-12 3:15 ` Anup Patel
2023-06-12 4:11 ` Alistair Francis
2 siblings, 0 replies; 6+ messages in thread
From: Anup Patel @ 2023-06-12 3:15 UTC (permalink / raw)
To: Tommy Wu
Cc: qemu-devel, qemu-riscv, Frank Chang, Alistair Francis,
Mayuresh Chitale, Ivan Klokov
On Fri, Jun 9, 2023 at 11:29 AM Tommy Wu <tommy.wu@sifive.com> wrote:
>
> According to the `The RISC-V Advanced Interrupt Architecture`
> document, if register `mmsiaddrcfgh` of the domain has bit L set
> to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
> read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
>
> Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> hw/intc/riscv_aplic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index afc5b54dbb..4bdc6a5d1a 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -688,13 +688,13 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
> * domains).
> */
> if (aplic->num_children &&
> - !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> + !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> aplic->smsicfgaddr = value;
> }
> } else if (aplic->mmode && aplic->msimode &&
> (addr == APLIC_SMSICFGADDRH)) {
> if (aplic->num_children &&
> - !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> + !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
> }
> } else if ((APLIC_SETIP_BASE <= addr) &&
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
2023-06-09 5:59 [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Tommy Wu
2023-06-12 3:01 ` Alistair Francis
2023-06-12 3:15 ` Anup Patel
@ 2023-06-12 4:11 ` Alistair Francis
2023-06-19 9:24 ` Peter Maydell
2 siblings, 1 reply; 6+ messages in thread
From: Alistair Francis @ 2023-06-12 4:11 UTC (permalink / raw)
To: Tommy Wu
Cc: qemu-devel, qemu-riscv, Frank Chang, Alistair Francis, Anup Patel,
Mayuresh Chitale, Ivan Klokov
On Fri, Jun 9, 2023 at 4:01 PM Tommy Wu <tommy.wu@sifive.com> wrote:
>
> According to the `The RISC-V Advanced Interrupt Architecture`
> document, if register `mmsiaddrcfgh` of the domain has bit L set
> to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
> read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
>
> Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> hw/intc/riscv_aplic.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index afc5b54dbb..4bdc6a5d1a 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -688,13 +688,13 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,
> * domains).
> */
> if (aplic->num_children &&
> - !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> + !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> aplic->smsicfgaddr = value;
> }
> } else if (aplic->mmode && aplic->msimode &&
> (addr == APLIC_SMSICFGADDRH)) {
> if (aplic->num_children &&
> - !(aplic->smsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> + !(aplic->mmsicfgaddrH & APLIC_xMSICFGADDRH_L)) {
> aplic->smsicfgaddrH = value & APLIC_xMSICFGADDRH_VALID_MASK;
> }
> } else if ((APLIC_SETIP_BASE <= addr) &&
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
2023-06-12 4:11 ` Alistair Francis
@ 2023-06-19 9:24 ` Peter Maydell
2023-06-22 1:50 ` Alistair Francis
0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2023-06-19 9:24 UTC (permalink / raw)
To: Alistair Francis
Cc: Tommy Wu, qemu-devel, qemu-riscv, Frank Chang, Alistair Francis,
Anup Patel, Mayuresh Chitale, Ivan Klokov
On Mon, 12 Jun 2023 at 05:12, Alistair Francis <alistair23@gmail.com> wrote:
>
> On Fri, Jun 9, 2023 at 4:01 PM Tommy Wu <tommy.wu@sifive.com> wrote:
> >
> > According to the `The RISC-V Advanced Interrupt Architecture`
> > document, if register `mmsiaddrcfgh` of the domain has bit L set
> > to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
> > read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
> >
> > Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> > Reviewed-by: Frank Chang <frank.chang@sifive.com>
>
> Thanks!
>
> Applied to riscv-to-apply.next
If it hasn't gone in already, would you mind tweaking the
subject line so that it says which interrupt controller
the change is for ? (ie "hw/intc/riscv_aplic", not just "hw/intc".)
thanks
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
2023-06-19 9:24 ` Peter Maydell
@ 2023-06-22 1:50 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2023-06-22 1:50 UTC (permalink / raw)
To: Peter Maydell
Cc: Tommy Wu, qemu-devel, qemu-riscv, Frank Chang, Alistair Francis,
Anup Patel, Mayuresh Chitale, Ivan Klokov
On Mon, Jun 19, 2023 at 7:24 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 12 Jun 2023 at 05:12, Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Fri, Jun 9, 2023 at 4:01 PM Tommy Wu <tommy.wu@sifive.com> wrote:
> > >
> > > According to the `The RISC-V Advanced Interrupt Architecture`
> > > document, if register `mmsiaddrcfgh` of the domain has bit L set
> > > to one, then `smsiaddrcfg` and `smsiaddrcfgh` are locked as
> > > read-only alongside `mmsiaddrcfg` and `mmsiaddrcfgh`.
> > >
> > > Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
> > > Reviewed-by: Frank Chang <frank.chang@sifive.com>
> >
> > Thanks!
> >
> > Applied to riscv-to-apply.next
>
> If it hasn't gone in already, would you mind tweaking the
> subject line so that it says which interrupt controller
> the change is for ? (ie "hw/intc/riscv_aplic", not just "hw/intc".)
Sorry Peter, it's already in. I'll try to keep a closer eye on the
commit titles in future
Alistair
>
> thanks
> -- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
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2023-06-09 5:59 [PATCH] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Tommy Wu
2023-06-12 3:01 ` Alistair Francis
2023-06-12 3:15 ` Anup Patel
2023-06-12 4:11 ` Alistair Francis
2023-06-19 9:24 ` Peter Maydell
2023-06-22 1:50 ` Alistair Francis
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