* [PATCH v2 1/4] target/riscv: Remove unused 'instmap.h' header in translate.c
2023-06-28 6:32 [PATCH v2 0/4] target/riscv: Misc header cleanups Philippe Mathieu-Daudé
@ 2023-06-28 6:32 ` Philippe Mathieu-Daudé
2023-06-30 12:14 ` Daniel Henrique Barboza
2023-06-28 6:32 ` [PATCH v2 2/4] target/riscv: Restrict sysemu specific header to user emulation Philippe Mathieu-Daudé
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-06-28 6:32 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 98d54c5617..c0379af418 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -30,7 +30,6 @@
#include "exec/log.h"
#include "semihosting/semihost.h"
-#include "instmap.h"
#include "internals.h"
#define HELPER_H "helper.h"
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 1/4] target/riscv: Remove unused 'instmap.h' header in translate.c
2023-06-28 6:32 ` [PATCH v2 1/4] target/riscv: Remove unused 'instmap.h' header in translate.c Philippe Mathieu-Daudé
@ 2023-06-30 12:14 ` Daniel Henrique Barboza
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Henrique Barboza @ 2023-06-30 12:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei, qemu-riscv,
Alistair Francis
On 6/28/23 03:32, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/translate.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 98d54c5617..c0379af418 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -30,7 +30,6 @@
> #include "exec/log.h"
> #include "semihosting/semihost.h"
>
> -#include "instmap.h"
> #include "internals.h"
>
> #define HELPER_H "helper.h"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/4] target/riscv: Restrict sysemu specific header to user emulation
2023-06-28 6:32 [PATCH v2 0/4] target/riscv: Misc header cleanups Philippe Mathieu-Daudé
2023-06-28 6:32 ` [PATCH v2 1/4] target/riscv: Remove unused 'instmap.h' header in translate.c Philippe Mathieu-Daudé
@ 2023-06-28 6:32 ` Philippe Mathieu-Daudé
2023-06-30 12:15 ` Daniel Henrique Barboza
2023-06-28 6:32 ` [PATCH v2 3/4] target/riscv: Restrict 'rv128' machine to TCG accelerator Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-06-28 6:32 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.c | 8 +++++---
target/riscv/cpu_helper.c | 2 ++
target/riscv/csr.c | 2 ++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fb8458bf74..d9a3684b3e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -23,9 +23,13 @@
#include "qemu/log.h"
#include "cpu.h"
#include "cpu_vendorid.h"
+#ifndef CONFIG_USER_ONLY
#include "pmu.h"
-#include "internals.h"
#include "time_helper.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
+#endif
+#include "internals.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
@@ -33,8 +37,6 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "fpu/softfloat-helpers.h"
-#include "sysemu/kvm.h"
-#include "kvm_riscv.h"
#include "tcg/tcg.h"
/* RISC-V CPU definitions */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 55c36025d7..3c28396eaf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -28,7 +28,9 @@
#include "tcg/tcg-op.h"
#include "trace.h"
#include "semihosting/common-semi.h"
+#ifndef CONFIG_USER_ONLY
#include "sysemu/cpu-timers.h"
+#endif
#include "cpu_bits.h"
#include "debug.h"
#include "tcg/oversized-guest.h"
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ea7585329e..e5737dcf58 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -21,8 +21,10 @@
#include "qemu/log.h"
#include "qemu/timer.h"
#include "cpu.h"
+#ifndef CONFIG_USER_ONLY
#include "pmu.h"
#include "time_helper.h"
+#endif
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
#include "exec/tb-flush.h"
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 2/4] target/riscv: Restrict sysemu specific header to user emulation
2023-06-28 6:32 ` [PATCH v2 2/4] target/riscv: Restrict sysemu specific header to user emulation Philippe Mathieu-Daudé
@ 2023-06-30 12:15 ` Daniel Henrique Barboza
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Henrique Barboza @ 2023-06-30 12:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei, qemu-riscv,
Alistair Francis
On 6/28/23 03:32, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 8 +++++---
> target/riscv/cpu_helper.c | 2 ++
> target/riscv/csr.c | 2 ++
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fb8458bf74..d9a3684b3e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -23,9 +23,13 @@
> #include "qemu/log.h"
> #include "cpu.h"
> #include "cpu_vendorid.h"
> +#ifndef CONFIG_USER_ONLY
> #include "pmu.h"
> -#include "internals.h"
> #include "time_helper.h"
> +#include "sysemu/kvm.h"
> +#include "kvm_riscv.h"
> +#endif
> +#include "internals.h"
> #include "exec/exec-all.h"
> #include "qapi/error.h"
> #include "qapi/visitor.h"
> @@ -33,8 +37,6 @@
> #include "hw/qdev-properties.h"
> #include "migration/vmstate.h"
> #include "fpu/softfloat-helpers.h"
> -#include "sysemu/kvm.h"
> -#include "kvm_riscv.h"
> #include "tcg/tcg.h"
>
> /* RISC-V CPU definitions */
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 55c36025d7..3c28396eaf 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -28,7 +28,9 @@
> #include "tcg/tcg-op.h"
> #include "trace.h"
> #include "semihosting/common-semi.h"
> +#ifndef CONFIG_USER_ONLY
> #include "sysemu/cpu-timers.h"
> +#endif
> #include "cpu_bits.h"
> #include "debug.h"
> #include "tcg/oversized-guest.h"
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ea7585329e..e5737dcf58 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -21,8 +21,10 @@
> #include "qemu/log.h"
> #include "qemu/timer.h"
> #include "cpu.h"
> +#ifndef CONFIG_USER_ONLY
> #include "pmu.h"
> #include "time_helper.h"
> +#endif
> #include "qemu/main-loop.h"
> #include "exec/exec-all.h"
> #include "exec/tb-flush.h"
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/4] target/riscv: Restrict 'rv128' machine to TCG accelerator
2023-06-28 6:32 [PATCH v2 0/4] target/riscv: Misc header cleanups Philippe Mathieu-Daudé
2023-06-28 6:32 ` [PATCH v2 1/4] target/riscv: Remove unused 'instmap.h' header in translate.c Philippe Mathieu-Daudé
2023-06-28 6:32 ` [PATCH v2 2/4] target/riscv: Restrict sysemu specific header to user emulation Philippe Mathieu-Daudé
@ 2023-06-28 6:32 ` Philippe Mathieu-Daudé
2023-06-30 12:15 ` Daniel Henrique Barboza
2023-06-28 6:32 ` [PATCH v2 4/4] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu Philippe Mathieu-Daudé
2023-07-03 1:29 ` [PATCH v2 0/4] target/riscv: Misc header cleanups Alistair Francis
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-06-28 6:32 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Philippe Mathieu-Daudé
We only build for 32/64-bit hosts, so TCG is required for
128-bit targets.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d9a3684b3e..5762ff68b4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -476,6 +476,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
#endif
}
+#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
if (qemu_tcg_mttcg_enabled()) {
@@ -494,7 +495,10 @@ static void rv128_base_cpu_init(Object *obj)
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
}
-#else
+#endif
+
+#else /* !TARGET_RISCV64 */
+
static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -576,7 +580,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
cpu->cfg.ext_icsr = true;
cpu->cfg.pmp = true;
}
-#endif
+#endif /* !TARGET_RISCV64 */
#if defined(CONFIG_KVM)
static void riscv_host_cpu_init(Object *obj)
@@ -1951,8 +1955,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
+#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
-#endif
+#endif /* CONFIG_TCG */
+#endif /* TARGET_RISCV64 */
};
DEFINE_TYPES(riscv_cpu_type_infos)
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 3/4] target/riscv: Restrict 'rv128' machine to TCG accelerator
2023-06-28 6:32 ` [PATCH v2 3/4] target/riscv: Restrict 'rv128' machine to TCG accelerator Philippe Mathieu-Daudé
@ 2023-06-30 12:15 ` Daniel Henrique Barboza
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Henrique Barboza @ 2023-06-30 12:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei, qemu-riscv,
Alistair Francis
On 6/28/23 03:32, Philippe Mathieu-Daudé wrote:
> We only build for 32/64-bit hosts, so TCG is required for
> 128-bit targets.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d9a3684b3e..5762ff68b4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -476,6 +476,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
> #endif
> }
>
> +#ifdef CONFIG_TCG
> static void rv128_base_cpu_init(Object *obj)
> {
> if (qemu_tcg_mttcg_enabled()) {
> @@ -494,7 +495,10 @@ static void rv128_base_cpu_init(Object *obj)
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> #endif
> }
> -#else
> +#endif
> +
> +#else /* !TARGET_RISCV64 */
> +
> static void rv32_base_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -576,7 +580,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> cpu->cfg.ext_icsr = true;
> cpu->cfg.pmp = true;
> }
> -#endif
> +#endif /* !TARGET_RISCV64 */
>
> #if defined(CONFIG_KVM)
> static void riscv_host_cpu_init(Object *obj)
> @@ -1951,8 +1955,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
> +#ifdef CONFIG_TCG
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> -#endif
> +#endif /* CONFIG_TCG */
> +#endif /* TARGET_RISCV64 */
> };
>
> DEFINE_TYPES(riscv_cpu_type_infos)
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 4/4] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu
2023-06-28 6:32 [PATCH v2 0/4] target/riscv: Misc header cleanups Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2023-06-28 6:32 ` [PATCH v2 3/4] target/riscv: Restrict 'rv128' machine to TCG accelerator Philippe Mathieu-Daudé
@ 2023-06-28 6:32 ` Philippe Mathieu-Daudé
2023-06-30 12:15 ` Daniel Henrique Barboza
2023-07-03 1:29 ` [PATCH v2 0/4] target/riscv: Misc header cleanups Alistair Francis
4 siblings, 1 reply; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-06-28 6:32 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis,
Philippe Mathieu-Daudé
riscv_cpu_do_interrupt() is not reachable on user emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.h | 5 +++--
target/riscv/cpu_helper.c | 7 ++-----
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index cc20ee25a7..ab6aa7e3ea 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -409,7 +409,6 @@ extern const char * const riscv_int_regnamesh[];
extern const char * const riscv_fpr_regnames[];
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
-void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, DumpState *s);
int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
@@ -442,6 +441,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
+void riscv_cpu_do_interrupt(CPUState *cpu);
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@@ -465,7 +465,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
void *rmw_fn_arg);
RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
-#endif
+#endif /* !CONFIG_USER_ONLY */
+
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3c28396eaf..3f5ba2b4ef 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1580,7 +1580,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
return xinsn;
}
-#endif /* !CONFIG_USER_ONLY */
/*
* Handle Traps
@@ -1590,8 +1589,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
*/
void riscv_cpu_do_interrupt(CPUState *cs)
{
-#if !defined(CONFIG_USER_ONLY)
-
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
bool write_gva = false;
@@ -1784,6 +1781,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->two_stage_lookup = false;
env->two_stage_indirect_lookup = false;
-#endif
- cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
}
+
+#endif /* !CONFIG_USER_ONLY */
--
2.38.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v2 4/4] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu
2023-06-28 6:32 ` [PATCH v2 4/4] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu Philippe Mathieu-Daudé
@ 2023-06-30 12:15 ` Daniel Henrique Barboza
0 siblings, 0 replies; 10+ messages in thread
From: Daniel Henrique Barboza @ 2023-06-30 12:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei, qemu-riscv,
Alistair Francis
On 6/28/23 03:32, Philippe Mathieu-Daudé wrote:
> riscv_cpu_do_interrupt() is not reachable on user emulation.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.h | 5 +++--
> target/riscv/cpu_helper.c | 7 ++-----
> 2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index cc20ee25a7..ab6aa7e3ea 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -409,7 +409,6 @@ extern const char * const riscv_int_regnamesh[];
> extern const char * const riscv_fpr_regnames[];
>
> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
> -void riscv_cpu_do_interrupt(CPUState *cpu);
> int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
> int cpuid, DumpState *s);
> int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
> @@ -442,6 +441,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
> #define cpu_mmu_index riscv_cpu_mmu_index
>
> #ifndef CONFIG_USER_ONLY
> +void riscv_cpu_do_interrupt(CPUState *cpu);
> void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> vaddr addr, unsigned size,
> MMUAccessType access_type,
> @@ -465,7 +465,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
> void *rmw_fn_arg);
>
> RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
> -#endif
> +#endif /* !CONFIG_USER_ONLY */
> +
> void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>
> void riscv_translate_init(void);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 3c28396eaf..3f5ba2b4ef 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1580,7 +1580,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
>
> return xinsn;
> }
> -#endif /* !CONFIG_USER_ONLY */
>
> /*
> * Handle Traps
> @@ -1590,8 +1589,6 @@ static target_ulong riscv_transformed_insn(CPURISCVState *env,
> */
> void riscv_cpu_do_interrupt(CPUState *cs)
> {
> -#if !defined(CONFIG_USER_ONLY)
> -
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> bool write_gva = false;
> @@ -1784,6 +1781,6 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>
> env->two_stage_lookup = false;
> env->two_stage_indirect_lookup = false;
> -#endif
> - cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
> }
> +
> +#endif /* !CONFIG_USER_ONLY */
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/4] target/riscv: Misc header cleanups
2023-06-28 6:32 [PATCH v2 0/4] target/riscv: Misc header cleanups Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2023-06-28 6:32 ` [PATCH v2 4/4] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu Philippe Mathieu-Daudé
@ 2023-07-03 1:29 ` Alistair Francis
4 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2023-07-03 1:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Bin Meng, Palmer Dabbelt, Weiwei Li, Liu Zhiwei,
Daniel Henrique Barboza, qemu-riscv, Alistair Francis
On Wed, Jun 28, 2023 at 4:34 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> As requested by Daniel in [1], these patches are extracted from
> my "target/riscv: Allow building without TCG (KVM-only so far)"
> series and cleanly rebased onto Alistair's riscv-to-apply.next.
>
> [1] https://lore.kernel.org/qemu-devel/59b5b342-8940-5ac1-0cec-8c136c4916d8@ventanamicro.com/
> [2] https://lore.kernel.org/qemu-devel/20230626232007.8933-1-philmd@linaro.org/
>
> Philippe Mathieu-Daudé (4):
> target/riscv: Remove unused 'instmap.h' header in translate.c
> target/riscv: Restrict sysemu specific header to user emulation
> target/riscv: Restrict 'rv128' machine to TCG accelerator
> target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu
Acked-by: Alistair Francis <alistair.francis@wdc.com>
But this doesn't apply on the latest riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 5 +++--
> target/riscv/cpu.c | 20 ++++++++++++++------
> target/riscv/cpu_helper.c | 9 ++++-----
> target/riscv/csr.c | 2 ++
> target/riscv/translate.c | 1 -
> 5 files changed, 23 insertions(+), 14 deletions(-)
>
> --
> 2.38.1
>
>
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