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Thu, 17 Mar 2022 19:17:40 -0700 (PDT) MIME-Version: 1.0 References: <20220315065529.62198-1-bmeng.cn@gmail.com> <20220315065529.62198-7-bmeng.cn@gmail.com> In-Reply-To: <20220315065529.62198-7-bmeng.cn@gmail.com> From: Alistair Francis Date: Fri, 18 Mar 2022 12:17:14 +1000 Message-ID: Subject: Re: [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature To: Bin Meng Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::12b (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::12b; envelope-from=alistair23@gmail.com; helo=mail-il1-x12b.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Alistair Francis , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Mar 15, 2022 at 5:02 PM Bin Meng wrote: > > From: Bin Meng > > Turn on native debug feature by default for all CPUs. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > (no changes since v3) > > Changes in v3: > - enable debug feature by default for all CPUs > > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ba9cc3bcd6..08266b163d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -788,7 +788,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), > + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > > DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > -- > 2.25.1 > >