* [PATCH] include/hw/riscv/opentitan: update opentitan IRQs
@ 2023-01-23 0:05 Wilfred Mallawa
2023-01-23 2:53 ` Alistair Francis
0 siblings, 1 reply; 2+ messages in thread
From: Wilfred Mallawa @ 2023-01-23 0:05 UTC (permalink / raw)
To: Alistair.Francis, palmer, bin.meng, qemu-riscv
Cc: qemu-devel, Wilfred Mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.
OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
include/hw/riscv/opentitan.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 7659d1bc5b..235728b9cc 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -108,11 +108,11 @@ enum {
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
- IBEX_TIMER_TIMEREXPIRED0_0 = 127,
- IBEX_SPI_HOST0_ERR_IRQ = 134,
- IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
- IBEX_SPI_HOST1_ERR_IRQ = 136,
- IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
+ IBEX_TIMER_TIMEREXPIRED0_0 = 124,
+ IBEX_SPI_HOST0_ERR_IRQ = 131,
+ IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132,
+ IBEX_SPI_HOST1_ERR_IRQ = 133,
+ IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134,
};
#endif
--
2.39.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] include/hw/riscv/opentitan: update opentitan IRQs
2023-01-23 0:05 [PATCH] include/hw/riscv/opentitan: update opentitan IRQs Wilfred Mallawa
@ 2023-01-23 2:53 ` Alistair Francis
0 siblings, 0 replies; 2+ messages in thread
From: Alistair Francis @ 2023-01-23 2:53 UTC (permalink / raw)
To: Wilfred Mallawa
Cc: Alistair.Francis, palmer, bin.meng, qemu-riscv, qemu-devel,
Wilfred Mallawa
On Mon, Jan 23, 2023 at 10:06 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Updates the opentitan IRQs to match the latest supported commit of
> Opentitan from TockOS.
>
> OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/riscv/opentitan.h | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 7659d1bc5b..235728b9cc 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -108,11 +108,11 @@ enum {
> IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
> IBEX_UART0_RX_TIMEOUT_IRQ = 7,
> IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
> - IBEX_TIMER_TIMEREXPIRED0_0 = 127,
> - IBEX_SPI_HOST0_ERR_IRQ = 134,
> - IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
> - IBEX_SPI_HOST1_ERR_IRQ = 136,
> - IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
> + IBEX_TIMER_TIMEREXPIRED0_0 = 124,
> + IBEX_SPI_HOST0_ERR_IRQ = 131,
> + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132,
> + IBEX_SPI_HOST1_ERR_IRQ = 133,
> + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134,
> };
>
> #endif
> --
> 2.39.0
>
>
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