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* [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s
@ 2024-10-30  4:35 Anton Blanchard
  2024-10-30 17:54 ` Daniel Henrique Barboza
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Anton Blanchard @ 2024-10-30  4:35 UTC (permalink / raw)
  To: qemu-riscv, qemu-devel
  Cc: Anton Blanchard, Palmer Dabbelt, Alistair Francis, Bin Meng,
	Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei

vcompress packs vl or less fields into vd, so the tail starts after the
last packed field. This could be more clearly expressed in the ISA,
but for now this thread helps to explain it:

https://github.com/riscv/riscv-v-spec/issues/796

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
---
 target/riscv/vector_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 072bd444b1..ccb32e6122 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5132,7 +5132,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
     }                                                                     \
     env->vstart = 0;                                                      \
     /* set tail elements to 1s */                                         \
-    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
+    vext_set_elems_1s(vd, vta, num * esz, total_elems * esz);             \
 }
 
 /* Compress into vd elements of vs2 where vs1 is enabled */
-- 
2.34.1



^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s
  2024-10-30  4:35 [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s Anton Blanchard
@ 2024-10-30 17:54 ` Daniel Henrique Barboza
  2024-10-31  1:21 ` Alistair Francis
  2024-10-31  2:22 ` Alistair Francis
  2 siblings, 0 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2024-10-30 17:54 UTC (permalink / raw)
  To: Anton Blanchard, qemu-riscv, qemu-devel
  Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei



On 10/30/24 1:35 AM, Anton Blanchard wrote:
> vcompress packs vl or less fields into vd, so the tail starts after the
> last packed field. This could be more clearly expressed in the ISA,
> but for now this thread helps to explain it:
> 
> https://github.com/riscv/riscv-v-spec/issues/796
> 
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/vector_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 072bd444b1..ccb32e6122 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5132,7 +5132,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
>       }                                                                     \
>       env->vstart = 0;                                                      \
>       /* set tail elements to 1s */                                         \
> -    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
> +    vext_set_elems_1s(vd, vta, num * esz, total_elems * esz);             \
>   }
>   
>   /* Compress into vd elements of vs2 where vs1 is enabled */


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s
  2024-10-30  4:35 [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s Anton Blanchard
  2024-10-30 17:54 ` Daniel Henrique Barboza
@ 2024-10-31  1:21 ` Alistair Francis
  2024-10-31  2:22 ` Alistair Francis
  2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2024-10-31  1:21 UTC (permalink / raw)
  To: Anton Blanchard
  Cc: qemu-riscv, qemu-devel, Palmer Dabbelt, Alistair Francis,
	Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei

On Wed, Oct 30, 2024 at 2:37 PM Anton Blanchard <antonb@tenstorrent.com> wrote:
>
> vcompress packs vl or less fields into vd, so the tail starts after the
> last packed field. This could be more clearly expressed in the ISA,
> but for now this thread helps to explain it:
>
> https://github.com/riscv/riscv-v-spec/issues/796
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/vector_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 072bd444b1..ccb32e6122 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5132,7 +5132,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
>      }                                                                     \
>      env->vstart = 0;                                                      \
>      /* set tail elements to 1s */                                         \
> -    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
> +    vext_set_elems_1s(vd, vta, num * esz, total_elems * esz);             \
>  }
>
>  /* Compress into vd elements of vs2 where vs1 is enabled */
> --
> 2.34.1
>
>


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s
  2024-10-30  4:35 [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s Anton Blanchard
  2024-10-30 17:54 ` Daniel Henrique Barboza
  2024-10-31  1:21 ` Alistair Francis
@ 2024-10-31  2:22 ` Alistair Francis
  2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2024-10-31  2:22 UTC (permalink / raw)
  To: Anton Blanchard
  Cc: qemu-riscv, qemu-devel, Palmer Dabbelt, Alistair Francis,
	Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei

On Wed, Oct 30, 2024 at 2:37 PM Anton Blanchard <antonb@tenstorrent.com> wrote:
>
> vcompress packs vl or less fields into vd, so the tail starts after the
> last packed field. This could be more clearly expressed in the ISA,
> but for now this thread helps to explain it:
>
> https://github.com/riscv/riscv-v-spec/issues/796
>
> Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/vector_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 072bd444b1..ccb32e6122 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5132,7 +5132,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2,               \
>      }                                                                     \
>      env->vstart = 0;                                                      \
>      /* set tail elements to 1s */                                         \
> -    vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz);              \
> +    vext_set_elems_1s(vd, vta, num * esz, total_elems * esz);             \
>  }
>
>  /* Compress into vd elements of vs2 where vs1 is enabled */
> --
> 2.34.1
>
>


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2024-10-31  2:23 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2024-10-30  4:35 [PATCH v2] target/riscv: Fix vcompress with rvv_ta_all_1s Anton Blanchard
2024-10-30 17:54 ` Daniel Henrique Barboza
2024-10-31  1:21 ` Alistair Francis
2024-10-31  2:22 ` Alistair Francis

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