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From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v4 20/20] target/riscv: Enable uxl field write
Date: Fri, 19 Nov 2021 22:55:52 +1000	[thread overview]
Message-ID: <CAKmqyKOrFTekP+JM+EGr7HLZ-MS2USjSzByRmMS+LbsRxV=rvQ@mail.gmail.com> (raw)
In-Reply-To: <20211111155149.58172-21-zhiwei_liu@c-sky.com>

On Fri, Nov 12, 2021 at 2:14 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu_bits.h | 2 ++
>  target/riscv/csr.c      | 8 +++++---
>  2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 9913fa9f77..5106f0e769 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -413,6 +413,8 @@ typedef enum {
>  #define SSTATUS_SUM         0x00040000 /* since: priv-1.10 */
>  #define SSTATUS_MXR         0x00080000
>
> +#define SSTATUS64_UXL       0x0000000300000000ULL
> +
>  #define SSTATUS32_SD        0x80000000
>  #define SSTATUS64_SD        0x8000000000000000ULL
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8f8f170768..e79532053a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>           * RV32: MPV and GVA are not in mstatus. The current plan is to
>           * add them to mstatush. For now, we just don't support it.
>           */
> -        mask |= MSTATUS_MPV | MSTATUS_GVA;
> +        mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
>      }
>
>      mstatus = (mstatus & ~mask) | (val & mask);
>
>      if (riscv_cpu_mxl(env) == MXL_RV64) {
> -        /* SXL and UXL fields are for now read only */
> +        /* SXL fields are for now read only */
>          mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
> -        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
>      }
>      env->mstatus = mstatus;
>
> @@ -840,6 +839,9 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
>                                      target_ulong val)
>  {
>      target_ulong mask = (sstatus_v1_10_mask);
> +    if (cpu_get_xl(env) != MXL_RV32) {
> +        mask |= SSTATUS64_UXL;
> +    }
>      target_ulong newval = (env->mstatus & ~mask) | (val & mask);
>      return write_mstatus(env, CSR_MSTATUS, newval);
>  }
> --
> 2.25.1
>
>


  parent reply	other threads:[~2021-11-19 12:58 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-11 15:51 [PATCH v4 00/20] Support UXL filed in xstatus LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 01/20] target/riscv: Don't save pc when exception return LIU Zhiwei
2021-11-15  4:25   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2021-11-15  4:26   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2021-11-15  4:27   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2021-11-16  0:08   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2021-11-16  3:12   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 06/20] target/riscv: Relax debug check for pm write LIU Zhiwei
2021-11-16  3:13   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2021-11-16  3:14   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 08/20] target/riscv: Create current pm fields in env LIU Zhiwei
2021-11-19  4:22   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2021-11-19  4:29   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 10/20] target/riscv: Calculate address according to XLEN LIU Zhiwei
2021-11-19  4:32   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2021-11-19  4:51   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 12/20] target/riscv: Split out the vill from vtype LIU Zhiwei
2021-11-19  4:55   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 13/20] target/riscv: Fix RESERVED field length in VTYPE LIU Zhiwei
2021-11-19  4:56   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 14/20] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2021-11-19 12:40   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 15/20] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2021-11-19 12:33   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 16/20] target/riscv: Ajdust vector atomic check with XLEN LIU Zhiwei
2021-11-19 12:34   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 17/20] target/riscv: Fix check range for first fault only LIU Zhiwei
2021-11-19 12:42   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 18/20] target/riscv: Adjust vector address with mask LIU Zhiwei
2021-11-19 12:46   ` Alistair Francis
2021-11-11 15:51 ` [PATCH v4 19/20] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2021-11-11 15:51 ` [PATCH v4 20/20] target/riscv: Enable uxl field write LIU Zhiwei
2021-11-11 18:23   ` Richard Henderson
2021-11-19 12:55   ` Alistair Francis [this message]
2021-11-19 12:57 ` [PATCH v4 00/20] Support UXL filed in xstatus Alistair Francis
2021-11-19 13:44   ` LIU Zhiwei

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