From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49660) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fBn6L-0002U0-He for qemu-devel@nongnu.org; Thu, 26 Apr 2018 16:02:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fBn6K-0007Co-Fg for qemu-devel@nongnu.org; Thu, 26 Apr 2018 16:02:45 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:43638) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fBn6K-0007BL-7Z for qemu-devel@nongnu.org; Thu, 26 Apr 2018 16:02:44 -0400 Received: by mail-lf0-x241.google.com with SMTP id g12-v6so16449798lfb.10 for ; Thu, 26 Apr 2018 13:02:44 -0700 (PDT) MIME-Version: 1.0 References: <1524699938-6764-1-git-send-email-mjc@sifive.com> <1524699938-6764-20-git-send-email-mjc@sifive.com> In-Reply-To: <1524699938-6764-20-git-send-email-mjc@sifive.com> From: Alistair Francis Date: Thu, 26 Apr 2018 20:02:17 +0000 Message-ID: Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH v8 19/35] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Clark Cc: "qemu-devel@nongnu.org Developers" , Sagar Karandikar , Bastian Koppelmann , palmer@sifive.com, Alistair Francis , patches@groups.riscv.org On Wed, Apr 25, 2018 at 5:10 PM Michael Clark wrote: > The mstatus.MXR alias in sstatus should only be writable > by S-mode if the privileged ISA version >= v1.10. Also MXR > was masked in sstatus CSR read but not sstatus CSR writes. > Now we correctly mask sstatus.mxr in both read and write. > Cc: Sagar Karandikar > Cc: Bastian Koppelmann > Cc: Palmer Dabbelt > Cc: Alistair Francis > Signed-off-by: Michael Clark Reviewed-by: Alistair Francis Alistair > --- > target/riscv/op_helper.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index b81b9b6..88c263a 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -236,7 +236,10 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, > target_ulong ms = env->mstatus; > target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE > | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS > - | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; > + | SSTATUS_SUM | SSTATUS_SD; > + if (env->priv_ver >= PRIV_VERSION_1_10_0) { > + mask |= SSTATUS_MXR; > + } > ms = (ms & ~mask) | (val_to_write & mask); > csr_write_helper(env, ms, CSR_MSTATUS); > break; > @@ -439,7 +442,7 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) > case CSR_SSTATUS: { > target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE > | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS > - | SSTATUS_SUM | SSTATUS_SD; > + | SSTATUS_SUM | SSTATUS_SD; > if (env->priv_ver >= PRIV_VERSION_1_10_0) { > mask |= SSTATUS_MXR; > } > -- > 2.7.0