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To: LIU Zhiwei Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92a; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Oct 7, 2024 at 1:35=E2=80=AFPM LIU Zhiwei wrote: > > From: TANG Tiancheng > > CSR satp is SXLEN bits in length and always has the $layout determined by > the SXL configuration, regardless of the current XLEN. > > Only process CSR satp, as we still don't have a riscv_cpu_vsxl API > currently. > > Added sxl32 property to control sxlen as 32 in s-mode for QEMU RV64. > > Signed-off-by: TANG Tiancheng > Fixes: c7b9517188 (RISC-V: Implement modular CSR helper interface) > Reviewed-by: Liu Zhiwei > --- > target/riscv/cpu_cfg.h | 4 ++++ > target/riscv/csr.c | 25 +++++++++++++++++++------ > 2 files changed, 23 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 8b272fb826..cdbd2afe29 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -173,6 +173,10 @@ struct RISCVCPUConfig { > bool short_isa_string; > > #ifndef CONFIG_USER_ONLY > + /* > + * true when RV64 QEMU running with mxlen=3D=3D64 but sxlen=3D=3D32. > + */ > + bool sxl32; > RISCVSATPMap satp_mode; > #endif > }; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index b33cc1ec23..93a5cf87ed 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1504,16 +1504,29 @@ static RISCVException read_mstatus(CPURISCVState = *env, int csrno, > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > - uint64_t mode_supported =3D riscv_cpu_cfg(env)->satp_mode.map; > + uint64_t mode_supported =3D 0; > + if (riscv_cpu_cfg(env)->sxl32 && (riscv_cpu_mxl(env) !=3D MXL_RV32))= { This should be using the actual SXLEN values, not this special property. What happens if the property is set to false but the guest software sets SXLEN to 32-bits? This will break Alistair > + mode_supported =3D (1 << VM_1_10_MBARE) | (1 << VM_1_10_SV32); > + } else { > + mode_supported =3D riscv_cpu_cfg(env)->satp_mode.map; > + } > return get_field(mode_supported, (1 << vm)); > } > > static target_ulong legalize_xatp(CPURISCVState *env, target_ulong old_x= atp, > - target_ulong val) > + target_ulong val, int csrno) > { > target_ulong mask; > bool vm; > - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { > + RISCVMXL xl; > + > + if (csrno =3D=3D CSR_SATP) { > + xl =3D riscv_cpu_sxl(env); > + } else { > + xl =3D riscv_cpu_mxl(env); > + } > + > + if (xl =3D=3D MXL_RV32) { > vm =3D validate_vm(env, get_field(val, SATP32_MODE)); > mask =3D (val ^ old_xatp) & (SATP32_MODE | SATP32_ASID | SATP32_= PPN); > } else { > @@ -3316,7 +3329,7 @@ static RISCVException write_satp(CPURISCVState *env= , int csrno, > return RISCV_EXCP_NONE; > } > > - env->satp =3D legalize_xatp(env, env->satp, val); > + env->satp =3D legalize_xatp(env, env->satp, val, csrno); > return RISCV_EXCP_NONE; > } > > @@ -3834,7 +3847,7 @@ static RISCVException read_hgatp(CPURISCVState *env= , int csrno, > static RISCVException write_hgatp(CPURISCVState *env, int csrno, > target_ulong val) > { > - env->hgatp =3D legalize_xatp(env, env->hgatp, val); > + env->hgatp =3D legalize_xatp(env, env->hgatp, val, csrno); > return RISCV_EXCP_NONE; > } > > @@ -4116,7 +4129,7 @@ static RISCVException read_vsatp(CPURISCVState *env= , int csrno, > static RISCVException write_vsatp(CPURISCVState *env, int csrno, > target_ulong val) > { > - env->vsatp =3D legalize_xatp(env, env->vsatp, val); > + env->vsatp =3D legalize_xatp(env, env->vsatp, val, csrno); > return RISCV_EXCP_NONE; > } > > -- > 2.43.0 > >