From: Alistair Francis <alistair23@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Liviu Ionescu <ilg@livius.net>,
Michael Davidsaver <mdavidsaver@gmail.com>,
Patch Tracking <patches@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 4/6] hw/registerfields.h: Pull FIELD etc macros out of hw/register.h
Date: Fri, 20 Jan 2017 11:04:18 -0800 [thread overview]
Message-ID: <CAKmqyKOwzNj827103eSYZp6wAbsn4Ymvit-ZSOV9J7dLRgvO1A@mail.gmail.com> (raw)
In-Reply-To: <1484937883-1068-5-git-send-email-peter.maydell@linaro.org>
On Fri, Jan 20, 2017 at 10:44 AM, Peter Maydell
<peter.maydell@linaro.org> wrote:
> hw/register.h provides macros like FIELD which make it easy to define
> shift, mask and length constants for the fields within a register.
> Unfortunately register.h also includes a lot of other things, some
> of which will only compile in the softmmu build.
>
> Pull the FIELD macro and friends out into a separate header file,
> so they can be used in places like target/arm files which also
> get built in the user-only configs.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Looks good to me, I'm glad this is being used by others :)
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Thanks,
Alistair
> ---
> include/hw/register.h | 47 +----------------------------------
> include/hw/registerfields.h | 60 +++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 61 insertions(+), 46 deletions(-)
> create mode 100644 include/hw/registerfields.h
>
> diff --git a/include/hw/register.h b/include/hw/register.h
> index 8c12233..8bff5fb 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -13,6 +13,7 @@
>
> #include "hw/qdev-core.h"
> #include "exec/memory.h"
> +#include "hw/registerfields.h"
>
> typedef struct RegisterInfo RegisterInfo;
> typedef struct RegisterAccessInfo RegisterAccessInfo;
> @@ -206,50 +207,4 @@ RegisterInfoArray *register_init_block32(DeviceState *owner,
>
> void register_finalize_block(RegisterInfoArray *r_array);
>
> -/* Define constants for a 32 bit register */
> -
> -/* This macro will define A_FOO, for the byte address of a register
> - * as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
> - */
> -#define REG32(reg, addr) \
> - enum { A_ ## reg = (addr) }; \
> - enum { R_ ## reg = (addr) / 4 };
> -
> -/* Define SHIFT, LENGTH and MASK constants for a field within a register */
> -
> -/* This macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH
> - * constants for field BAR in register FOO.
> - */
> -#define FIELD(reg, field, shift, length) \
> - enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
> - enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
> - enum { R_ ## reg ## _ ## field ## _MASK = \
> - MAKE_64BIT_MASK(shift, length)};
> -
> -/* Extract a field from a register */
> -#define FIELD_EX32(storage, reg, field) \
> - extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> - R_ ## reg ## _ ## field ## _LENGTH)
> -
> -/* Extract a field from an array of registers */
> -#define ARRAY_FIELD_EX32(regs, reg, field) \
> - FIELD_EX32((regs)[R_ ## reg], reg, field)
> -
> -/* Deposit a register field.
> - * Assigning values larger then the target field will result in
> - * compilation warnings.
> - */
> -#define FIELD_DP32(storage, reg, field, val) ({ \
> - struct { \
> - unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
> - } v = { .v = val }; \
> - uint32_t d; \
> - d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> - R_ ## reg ## _ ## field ## _LENGTH, v.v); \
> - d; })
> -
> -/* Deposit a field to array of registers. */
> -#define ARRAY_FIELD_DP32(regs, reg, field, val) \
> - (regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val);
> -
> #endif
> diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
> new file mode 100644
> index 0000000..af101d5
> --- /dev/null
> +++ b/include/hw/registerfields.h
> @@ -0,0 +1,60 @@
> +/*
> + * Register Definition API: field macros
> + *
> + * Copyright (c) 2016 Xilinx Inc.
> + * Copyright (c) 2013 Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2. See
> + * the COPYING file in the top-level directory.
> + */
> +
> +#ifndef REGISTERFIELDS_H
> +#define REGISTERFIELDS_H
> +
> +/* Define constants for a 32 bit register */
> +
> +/* This macro will define A_FOO, for the byte address of a register
> + * as well as R_FOO for the uint32_t[] register number (A_FOO / 4).
> + */
> +#define REG32(reg, addr) \
> + enum { A_ ## reg = (addr) }; \
> + enum { R_ ## reg = (addr) / 4 };
> +
> +/* Define SHIFT, LENGTH and MASK constants for a field within a register */
> +
> +/* This macro will define FOO_BAR_MASK, FOO_BAR_SHIFT and FOO_BAR_LENGTH
> + * constants for field BAR in register FOO.
> + */
> +#define FIELD(reg, field, shift, length) \
> + enum { R_ ## reg ## _ ## field ## _SHIFT = (shift)}; \
> + enum { R_ ## reg ## _ ## field ## _LENGTH = (length)}; \
> + enum { R_ ## reg ## _ ## field ## _MASK = \
> + MAKE_64BIT_MASK(shift, length)};
> +
> +/* Extract a field from a register */
> +#define FIELD_EX32(storage, reg, field) \
> + extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> + R_ ## reg ## _ ## field ## _LENGTH)
> +
> +/* Extract a field from an array of registers */
> +#define ARRAY_FIELD_EX32(regs, reg, field) \
> + FIELD_EX32((regs)[R_ ## reg], reg, field)
> +
> +/* Deposit a register field.
> + * Assigning values larger then the target field will result in
> + * compilation warnings.
> + */
> +#define FIELD_DP32(storage, reg, field, val) ({ \
> + struct { \
> + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \
> + } v = { .v = val }; \
> + uint32_t d; \
> + d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, \
> + R_ ## reg ## _ ## field ## _LENGTH, v.v); \
> + d; })
> +
> +/* Deposit a field to array of registers. */
> +#define ARRAY_FIELD_DP32(regs, reg, field, val) \
> + (regs)[R_ ## reg] = FIELD_DP32((regs)[R_ ## reg], reg, field, val);
> +
> +#endif
> --
> 2.7.4
>
>
next prev parent reply other threads:[~2017-01-20 19:05 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-20 18:44 [Qemu-devel] [PATCH 0/6] ARMv7M: some simple bugfixes and cleanups Peter Maydell
2017-01-20 18:44 ` [Qemu-devel] [PATCH 1/6] armv7m: MRS/MSR: handle unprivileged access Peter Maydell
2017-01-24 16:25 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-01-24 16:51 ` Peter Maydell
2017-01-20 18:44 ` [Qemu-devel] [PATCH 2/6] armv7m: Replace armv7m.hack with unassigned_access handler Peter Maydell
2017-01-24 16:31 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-01-24 16:53 ` Peter Maydell
2017-01-20 18:44 ` [Qemu-devel] [PATCH 3/6] armv7m: Explicit error for bad vector table Peter Maydell
2017-01-24 16:43 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-01-20 18:44 ` [Qemu-devel] [PATCH 4/6] hw/registerfields.h: Pull FIELD etc macros out of hw/register.h Peter Maydell
2017-01-20 19:04 ` Alistair Francis [this message]
2017-01-24 16:43 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-01-20 18:44 ` [Qemu-devel] [PATCH 5/6] armv7m: Fix reads of CONTROL register bit 1 Peter Maydell
2017-01-24 16:58 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-01-24 17:04 ` Peter Maydell
2017-01-20 18:44 ` [Qemu-devel] [PATCH 6/6] armv7m: Clear FAULTMASK on return from non-NMI exceptions Peter Maydell
2017-01-24 16:59 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
2017-01-20 19:14 ` [Qemu-devel] [PATCH 0/6] ARMv7M: some simple bugfixes and cleanups no-reply
2017-01-24 17:00 ` [Qemu-devel] [Qemu-arm] " Alex Bennée
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