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Fri, 08 Jan 2021 15:34:36 -0800 (PST) MIME-Version: 1.0 References: <20201223192553.332508-1-atish.patra@wdc.com> <3542d26c042fd088114aa403612a58a643d45eaf.camel@wdc.com> In-Reply-To: <3542d26c042fd088114aa403612a58a643d45eaf.camel@wdc.com> From: Alistair Francis Date: Fri, 8 Jan 2021 15:34:10 -0800 Message-ID: Subject: Re: [PATCH v2] target/riscv/pmp: Raise exception if no PMP entry is configured To: Atish Patra Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::136; envelope-from=alistair23@gmail.com; helo=mail-il1-x136.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "qemu-riscv@nongnu.org" , "sagark@eecs.berkeley.edu" , "kbastian@mail.uni-paderborn.de" , Anup Patel , "qemu-devel@nongnu.org" , Alistair Francis , "palmer@dabbelt.com" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jan 7, 2021 at 11:02 AM Atish Patra wrote: > > On Thu, 2021-01-07 at 09:19 -0800, Alistair Francis wrote: > > On Wed, Dec 23, 2020 at 11:26 AM Atish Patra > > wrote: > > > > > > As per the privilege specification, any access from S/U mode should > > > fail > > > if no pmp region is configured. > > > > This doesn't sound right, the spec says: > > > > "If no PMP entry matches an S-mode or U-mode access, but at least one > > PMP entry is implemented, the access fails." > > > > I don't see anything saying that an access will fail if there are no > > PMP regions configred. > > > > It also says > > If at least one PMP entry is implemented, but all PMP entries=E2=80=99 A = fields > are set to OFF, then all S-mode and U-mode memory accesses will fail. > > My understanding is that if PMP is implemented in hardware, but not > configured, S/U-mode memory access should fail. At least that's how > hardware behave. Ah, I misinterpreted what implemented means. Reviewed-by: Alistair Francis Applied to riscv-to-apply.next Alistair > > > Alistair > > > > > > > > Signed-off-by: Atish Patra > > > --- > > > Changes from v2->v1 > > > 1. Removed the static from the function definition > > > --- > > > target/riscv/op_helper.c | 5 +++++ > > > target/riscv/pmp.c | 4 ++-- > > > target/riscv/pmp.h | 1 + > > > 3 files changed, 8 insertions(+), 2 deletions(-) > > > > > > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > > > index d55def76cffd..1eddcb94de7e 100644 > > > --- a/target/riscv/op_helper.c > > > +++ b/target/riscv/op_helper.c > > > @@ -150,6 +150,11 @@ target_ulong helper_mret(CPURISCVState *env, > > > target_ulong cpu_pc_deb) > > > > > > uint64_t mstatus =3D env->mstatus; > > > target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); > > > + > > > + if (!pmp_get_num_rules(env) && (prev_priv !=3D PRV_M)) { > > > + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, > > > GETPC()); > > > + } > > > + > > > target_ulong prev_virt =3D get_field(env->mstatus, MSTATUS_MPV); > > > mstatus =3D set_field(mstatus, MSTATUS_MIE, > > > get_field(mstatus, MSTATUS_MPIE)); > > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > > > index 2eda8e1e2f07..80d0334e1bfc 100644 > > > --- a/target/riscv/pmp.c > > > +++ b/target/riscv/pmp.c > > > @@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState > > > *env, uint32_t pmp_index) > > > /* > > > * Count the number of active rules. > > > */ > > > -static inline uint32_t pmp_get_num_rules(CPURISCVState *env) > > > +uint32_t pmp_get_num_rules(CPURISCVState *env) > > > { > > > return env->pmp_state.num_rules; > > > } > > > @@ -237,7 +237,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, > > > target_ulong addr, > > > > > > /* Short cut if no rules */ > > > if (0 =3D=3D pmp_get_num_rules(env)) { > > > - return true; > > > + return (env->priv =3D=3D PRV_M) ? true : false; > > > } > > > > > > if (size =3D=3D 0) { > > > diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h > > > index 6c6b4c9befe8..c8d5ef4a694e 100644 > > > --- a/target/riscv/pmp.h > > > +++ b/target/riscv/pmp.h > > > @@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, > > > hwaddr tlb_sa, > > > target_ulong *tlb_size); > > > void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); > > > void pmp_update_rule_nums(CPURISCVState *env); > > > +uint32_t pmp_get_num_rules(CPURISCVState *env); > > > > > > #endif > > > -- > > > 2.25.1 > > > > > > > > -- > Regards, > Atish