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From: Alistair Francis <alistair.francis@xilinx.com>
Date: Fri, 4 Sep 2015 11:32:51 -0700
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Subject: Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY
 SPCFC reset value
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>, Edgar Iglesias <edgar.iglesias@gmail.com>, Peter Crosthwaite <crosthwaitepeter@gmail.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Alistair Francis <alistair.francis@xilinx.com>

On Fri, Sep 4, 2015 at 11:12 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 4 September 2015 at 19:00, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
>> <edgar.iglesias@xilinx.com> wrote:
>>> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>>>> Bit 15 of the PHY Specific Status Register is reserved and
>>>> should remain 0. Fix the reset value to ensure that the 15th
>>>> bit is not set.
>>>>
>>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>>
>>> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>>
>> Thanks Edgar.
>>
>> Should this go via the ARM queue?
>
> I was planning to pick it up, unless Edgar would rather
> something else.

Great! Thanks Peter.

That's fine with me, just thought I would check.

Thanks,

Alistair

>
> -- PMM
>