* [PATCH] target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode
@ 2026-03-18 2:42 Jim Shu
2026-03-19 3:33 ` Alistair Francis
2026-03-19 3:40 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Jim Shu @ 2026-03-18 2:42 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Jim Shu, Max Chou
From Sscofpmf spec [1]:
- In M-mode, scountovf bit X is always readable.
- in VS mode, scountovf bit X is readable when mcounteren bit X and
hcounteren bit X are both set, and otherwise reads as zero.
[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/sscofpmf.adoc
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/csr.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5064483917..a75281539b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1599,6 +1599,7 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
int i;
*val = 0;
+ bool virt = env->virt_enabled;
/* Virtualize scountovf for counter delegation */
if (riscv_cpu_cfg(env)->ext_sscofpmf &&
@@ -1609,8 +1610,19 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
}
for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
- if ((get_field(env->mcounteren, BIT(i))) &&
- (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF)) {
+ if (env->priv < PRV_M) {
+ if (!get_field(env->mcounteren, BIT(i))) {
+ /* no mcounteren in S/HS-mode */
+ continue;
+ }
+
+ if (virt && !get_field(env->hcounteren, BIT(i))) {
+ /* no hcounteren in VS-mode */
+ continue;
+ }
+ }
+
+ if (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF) {
*val |= BIT(i);
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode
2026-03-18 2:42 [PATCH] target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode Jim Shu
@ 2026-03-19 3:33 ` Alistair Francis
2026-03-19 3:40 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2026-03-19 3:33 UTC (permalink / raw)
To: Jim Shu
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Max Chou
On Wed, Mar 18, 2026 at 12:44 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> From Sscofpmf spec [1]:
> - In M-mode, scountovf bit X is always readable.
> - in VS mode, scountovf bit X is readable when mcounteren bit X and
> hcounteren bit X are both set, and otherwise reads as zero.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/sscofpmf.adoc
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5064483917..a75281539b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1599,6 +1599,7 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
> int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
> int i;
> *val = 0;
> + bool virt = env->virt_enabled;
>
> /* Virtualize scountovf for counter delegation */
> if (riscv_cpu_cfg(env)->ext_sscofpmf &&
> @@ -1609,8 +1610,19 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
> }
>
> for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
> - if ((get_field(env->mcounteren, BIT(i))) &&
> - (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF)) {
> + if (env->priv < PRV_M) {
> + if (!get_field(env->mcounteren, BIT(i))) {
> + /* no mcounteren in S/HS-mode */
> + continue;
> + }
> +
> + if (virt && !get_field(env->hcounteren, BIT(i))) {
> + /* no hcounteren in VS-mode */
> + continue;
> + }
> + }
> +
> + if (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF) {
> *val |= BIT(i);
> }
> }
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode
2026-03-18 2:42 [PATCH] target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode Jim Shu
2026-03-19 3:33 ` Alistair Francis
@ 2026-03-19 3:40 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2026-03-19 3:40 UTC (permalink / raw)
To: Jim Shu
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, Max Chou
On Wed, Mar 18, 2026 at 12:44 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> From Sscofpmf spec [1]:
> - In M-mode, scountovf bit X is always readable.
> - in VS mode, scountovf bit X is readable when mcounteren bit X and
> hcounteren bit X are both set, and otherwise reads as zero.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/sscofpmf.adoc
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Signed-off-by: Max Chou <max.chou@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/csr.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5064483917..a75281539b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1599,6 +1599,7 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
> int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
> int i;
> *val = 0;
> + bool virt = env->virt_enabled;
>
> /* Virtualize scountovf for counter delegation */
> if (riscv_cpu_cfg(env)->ext_sscofpmf &&
> @@ -1609,8 +1610,19 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
> }
>
> for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
> - if ((get_field(env->mcounteren, BIT(i))) &&
> - (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF)) {
> + if (env->priv < PRV_M) {
> + if (!get_field(env->mcounteren, BIT(i))) {
> + /* no mcounteren in S/HS-mode */
> + continue;
> + }
> +
> + if (virt && !get_field(env->hcounteren, BIT(i))) {
> + /* no hcounteren in VS-mode */
> + continue;
> + }
> + }
> +
> + if (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF) {
> *val |= BIT(i);
> }
> }
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-03-18 2:42 [PATCH] target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode Jim Shu
2026-03-19 3:33 ` Alistair Francis
2026-03-19 3:40 ` Alistair Francis
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