From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cJOVV-00043Z-I9 for qemu-devel@nongnu.org; Tue, 20 Dec 2016 12:47:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cJOVU-0001Iq-OM for qemu-devel@nongnu.org; Tue, 20 Dec 2016 12:47:21 -0500 MIME-Version: 1.0 In-Reply-To: References: <1481625384-15077-1-git-send-email-peter.maydell@linaro.org> <1481625384-15077-23-git-send-email-peter.maydell@linaro.org> <20161213161152.GN9606@toto> From: Alistair Francis Date: Tue, 20 Dec 2016 09:46:47 -0800 Message-ID: Content-Type: text/plain; charset=UTF-8 Subject: Re: [Qemu-devel] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , Andrew Jones , qemu-arm , "qemu-devel@nongnu.org Developers" , Christoffer Dall , Patch Tracking On Tue, Dec 20, 2016 at 5:32 AM, Peter Maydell wrote: > On 19 December 2016 at 22:04, Alistair Francis wrote: >> On Tue, Dec 13, 2016 at 8:11 AM, Edgar E. Iglesias >> wrote: >>> On Tue, Dec 13, 2016 at 10:36:23AM +0000, Peter Maydell wrote: >>>> Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and >>>> Cortex-A57, since this is all now sufficiently implemented >>>> to work with the GICv3. We provide the usual CPU property >>>> to disable it for backwards compatibility with the older >>>> virt boards. >>>> >>>> In this commit, we disable the EL2 feature on the >>>> virt and ZynpMP boards, so there is no overall effect. >>>> Another commit will expose a board-level property to >>>> allow the user to enable EL2. > >>>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c >>>> index 0d86ba3..bc4e66b 100644 >>>> --- a/hw/arm/xlnx-zynqmp.c >>>> +++ b/hw/arm/xlnx-zynqmp.c >>>> @@ -258,6 +258,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) >>>> >>>> object_property_set_bool(OBJECT(&s->apu_cpu[i]), >>>> s->secure, "has_el3", NULL); >>>> + object_property_set_bool(OBJECT(&s->apu_cpu[i]), >>>> + false, "has_el2", NULL); >> >> Hey Peter, >> >> We would like this to be settable. I think just copying the s->secure >> (same as EL3) should be fine here. >> >> Let me know what is easier for you, if you want to just add an extra >> patch to enable it or if you want me to send a patch doing it? > > I'm not really set up to test the xilinx boards, so I'd rather > let you test and send the extra patch to enable it for them. Yeah, no worries. I'll sent a patch out to apply on top of this series. Thanks, Alistair > > thanks > -- PMM