From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV
Date: Thu, 15 Jul 2021 15:04:28 +1000 [thread overview]
Message-ID: <CAKmqyKP40vt2HeK_e8m1QqDsmiTpPzypyHjjGsGWRZ30OFBBCw@mail.gmail.com> (raw)
In-Reply-To: <20210709042608.883256-17-richard.henderson@linaro.org>
On Fri, Jul 9, 2021 at 2:43 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 79 +++++++------------------
> 1 file changed, 20 insertions(+), 59 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index a8e7272487..84a45fac38 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -27,27 +27,21 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> return false;
> }
>
> - s2 = tcg_temp_new();
> - dst = tcg_temp_new();
> + s2 = gpr_src(ctx, a->rs2);
> + dst = gpr_dst(ctx, a->rd);
>
> /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> if (a->rs1 == 0) {
> /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> s1 = tcg_constant_tl(RV_VLEN_MAX);
> } else {
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> + s1 = gpr_src(ctx, a->rs1);
> }
> - gen_get_gpr(s2, a->rs2);
> gen_helper_vsetvl(dst, cpu_env, s1, s2);
> - gen_set_gpr(a->rd, dst);
> +
> tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> lookup_and_goto_ptr(ctx);
> ctx->base.is_jmp = DISAS_NORETURN;
> -
> - tcg_temp_free(s1);
> - tcg_temp_free(s2);
> - tcg_temp_free(dst);
> return true;
> }
>
> @@ -60,23 +54,19 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
> }
>
> s2 = tcg_constant_tl(a->zimm);
> - dst = tcg_temp_new();
> + dst = gpr_dst(ctx, a->rd);
>
> /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> if (a->rs1 == 0) {
> /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> s1 = tcg_constant_tl(RV_VLEN_MAX);
> } else {
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> + s1 = gpr_src(ctx, a->rs1);
> }
> gen_helper_vsetvl(dst, cpu_env, s1, s2);
> - gen_set_gpr(a->rd, dst);
> +
> gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
> ctx->base.is_jmp = DISAS_NORETURN;
> -
> - tcg_temp_free(s1);
> - tcg_temp_free(dst);
> return true;
> }
>
> @@ -173,7 +163,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> - base = tcg_temp_new();
> + base = gpr_src(s, rs1);
>
> /*
> * As simd_desc supports at most 256 bytes, and in this implementation,
> @@ -184,7 +174,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
> */
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> - gen_get_gpr(base, rs1);
> tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
>
> @@ -192,7 +181,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>
> tcg_temp_free_ptr(dest);
> tcg_temp_free_ptr(mask);
> - tcg_temp_free(base);
> gen_set_label(over);
> return true;
> }
> @@ -330,12 +318,10 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
>
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> - base = tcg_temp_new();
> - stride = tcg_temp_new();
> + base = gpr_src(s, rs1);
> + stride = gpr_src(s, rs2);
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> - gen_get_gpr(base, rs1);
> - gen_get_gpr(stride, rs2);
> tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
>
> @@ -343,8 +329,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
>
> tcg_temp_free_ptr(dest);
> tcg_temp_free_ptr(mask);
> - tcg_temp_free(base);
> - tcg_temp_free(stride);
> gen_set_label(over);
> return true;
> }
> @@ -458,10 +442,9 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> index = tcg_temp_new_ptr();
> - base = tcg_temp_new();
> + base = gpr_src(s, rs1);
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> - gen_get_gpr(base, rs1);
> tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
> @@ -471,7 +454,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> tcg_temp_free_ptr(dest);
> tcg_temp_free_ptr(mask);
> tcg_temp_free_ptr(index);
> - tcg_temp_free(base);
> gen_set_label(over);
> return true;
> }
> @@ -589,10 +571,9 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> - base = tcg_temp_new();
> + base = gpr_src(s, rs1);
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> - gen_get_gpr(base, rs1);
> tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
>
> @@ -600,7 +581,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>
> tcg_temp_free_ptr(dest);
> tcg_temp_free_ptr(mask);
> - tcg_temp_free(base);
> gen_set_label(over);
> return true;
> }
> @@ -665,10 +645,9 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> index = tcg_temp_new_ptr();
> - base = tcg_temp_new();
> + base = gpr_src(s, rs1);
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> - gen_get_gpr(base, rs1);
> tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
> @@ -678,7 +657,6 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> tcg_temp_free_ptr(dest);
> tcg_temp_free_ptr(mask);
> tcg_temp_free_ptr(index);
> - tcg_temp_free(base);
> gen_set_label(over);
> return true;
> }
> @@ -862,8 +840,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> - src1 = tcg_temp_new();
> - gen_get_gpr(src1, rs1);
> + src1 = gpr_src(s, rs1);
>
> data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
> data = FIELD_DP32(data, VDATA, VM, vm);
> @@ -879,7 +856,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> tcg_temp_free_ptr(dest);
> tcg_temp_free_ptr(mask);
> tcg_temp_free_ptr(src2);
> - tcg_temp_free(src1);
> gen_set_label(over);
> return true;
> }
> @@ -905,15 +881,12 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
>
> if (a->vm && s->vl_eq_vlmax) {
> TCGv_i64 src1 = tcg_temp_new_i64();
> - TCGv tmp = tcg_temp_new();
>
> - gen_get_gpr(tmp, a->rs1);
> - tcg_gen_ext_tl_i64(src1, tmp);
> + tcg_gen_ext_tl_i64(src1, gpr_src(s, a->rs1));
> gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
> src1, MAXSZ(s), MAXSZ(s));
>
> tcg_temp_free_i64(src1);
> - tcg_temp_free(tmp);
> return true;
> }
> return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> @@ -1398,16 +1371,13 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
>
> if (a->vm && s->vl_eq_vlmax) {
> TCGv_i32 src1 = tcg_temp_new_i32();
> - TCGv tmp = tcg_temp_new();
>
> - gen_get_gpr(tmp, a->rs1);
> - tcg_gen_trunc_tl_i32(src1, tmp);
> + tcg_gen_trunc_tl_i32(src1, gpr_src(s, a->rs1));
> tcg_gen_extract_i32(src1, src1, 0, s->sew + 3);
> gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
> src1, MAXSZ(s), MAXSZ(s));
>
> tcg_temp_free_i32(src1);
> - tcg_temp_free(tmp);
> return true;
> }
> return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> @@ -1665,8 +1635,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> TCGLabel *over = gen_new_label();
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> - s1 = tcg_temp_new();
> - gen_get_gpr(s1, a->rs1);
> + s1 = gpr_src(s, a->rs1);
>
> if (s->vl_eq_vlmax) {
> tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
> @@ -1690,7 +1659,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> tcg_temp_free_i64(s1_i64);
> }
>
> - tcg_temp_free(s1);
> gen_set_label(over);
> return true;
> }
> @@ -2412,18 +2380,16 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
>
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> - dst = tcg_temp_new();
> + dst = gpr_dst(s, a->rd);
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
>
> gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
> - gen_set_gpr(a->rd, dst);
>
> tcg_temp_free_ptr(mask);
> tcg_temp_free_ptr(src2);
> - tcg_temp_free(dst);
> return true;
> }
> return false;
> @@ -2443,18 +2409,16 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
>
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> - dst = tcg_temp_new();
> + dst = gpr_dst(s, a->rd);
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
>
> gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
> - gen_set_gpr(a->rd, dst);
>
> tcg_temp_free_ptr(mask);
> tcg_temp_free_ptr(src2);
> - tcg_temp_free(dst);
> return true;
> }
> return false;
> @@ -2638,7 +2602,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
> static bool trans_vext_x_v(DisasContext *s, arg_r *a)
> {
> TCGv_i64 tmp = tcg_temp_new_i64();
> - TCGv dest = tcg_temp_new();
>
> if (a->rs1 == 0) {
> /* Special case vmv.x.s rd, vs2. */
> @@ -2648,10 +2611,8 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
> int vlmax = s->vlen >> (3 + s->sew);
> vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
> }
> - tcg_gen_trunc_i64_tl(dest, tmp);
> - gen_set_gpr(a->rd, dest);
>
> - tcg_temp_free(dest);
> + tcg_gen_trunc_i64_tl(gpr_dst(s, a->rd), tmp);
> tcg_temp_free_i64(tmp);
> return true;
> }
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-07-15 5:06 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-09 4:25 [PATCH 00/17] target/riscv: Use tcg_constant_* Richard Henderson
2021-07-09 4:25 ` [PATCH 01/17] " Richard Henderson
2021-07-09 5:41 ` Alistair Francis
2021-07-09 16:20 ` Philippe Mathieu-Daudé
2021-07-09 4:25 ` [PATCH 02/17] target/riscv: Introduce gpr_src, gpr_dst Richard Henderson
2021-07-09 5:45 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 03/17] target/riscv: Use gpr_{src,dst} in shift operations Richard Henderson
2021-07-13 4:10 ` [PATCH 03/17] target/riscv: Use gpr_{src, dst} " Alistair Francis
2021-07-09 4:25 ` [PATCH 04/17] target/riscv: Use gpr_{src, dst} in word division operations Richard Henderson
2021-07-13 4:11 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 05/17] target/riscv: Use gpr_{src, dst} and tcg_constant_tl in gen_grevi Richard Henderson
2021-07-13 4:12 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 06/17] target/riscv: Use gpr_src in branches Richard Henderson
2021-07-13 4:14 ` Alistair Francis
2021-07-09 4:25 ` [PATCH 07/17] target/riscv: Use gpr_{src,dst} for integer load/store Richard Henderson
2021-07-13 4:18 ` [PATCH 07/17] target/riscv: Use gpr_{src, dst} " Alistair Francis
2021-07-09 4:25 ` [PATCH 08/17] target/riscv: Use gpr_{src, dst} for word shift operations Richard Henderson
2021-07-15 4:49 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 09/17] target/riscv: Reorg csr instructions Richard Henderson
2021-07-23 5:00 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 10/17] target/riscv: Use gpr_{src,dst} for RVA Richard Henderson
2021-07-15 4:50 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 11/17] target/riscv: Use gpr_{src,dst} for RVB Richard Henderson
2021-07-15 4:52 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 12/17] target/riscv: Use gpr_{src,dst} for RVF Richard Henderson
2021-07-15 4:58 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 13/17] target/riscv: Use gpr_{src,dst} for RVD Richard Henderson
2021-07-15 5:00 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 14/17] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-07-23 5:02 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 15/17] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-07-15 5:02 ` Alistair Francis
2021-07-09 4:26 ` [PATCH 16/17] target/riscv: Use gpr_{src,dst} for RVV Richard Henderson
2021-07-15 5:04 ` Alistair Francis [this message]
2021-07-09 4:26 ` [PATCH 17/17] target/riscv: Remove gen_get_gpr Richard Henderson
2021-07-15 5:08 ` Alistair Francis
2021-07-15 11:21 ` [PATCH 00/17] target/riscv: Use tcg_constant_* LIU Zhiwei
2021-07-15 16:15 ` Richard Henderson
2021-07-17 3:59 ` LIU Zhiwei
2021-07-17 15:41 ` Richard Henderson
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