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Tue, 24 Mar 2026 18:57:34 -0700 (PDT) MIME-Version: 1.0 References: <20260321144554.606417-1-npiggin@gmail.com> <20260321144554.606417-3-npiggin@gmail.com> In-Reply-To: <20260321144554.606417-3-npiggin@gmail.com> From: Alistair Francis Date: Wed, 25 Mar 2026 11:57:07 +1000 X-Gm-Features: AQROBzDWJMTpsi4GA8nHlv7M_EMtUc1TCFdhhrs3SE-aNo8weE8iMNQTTj2DtQE Message-ID: Subject: Re: [PATCH v3 2/3] target/riscv: Fix vector whole ldst vstart check To: Nicholas Piggin Cc: qemu-riscv@nongnu.org, Laurent Vivier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org, Joel Stanley , Nicholas Joaquin , Ganesh Valliappan Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=alistair23@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Mar 22, 2026 at 12:47=E2=80=AFAM Nicholas Piggin wrote: > > The whole vector ldst instructions do not include a vstart check, so an > overflowed vstart can result in an underflowed memory address offset and > crash: > > accel/tcg/cputlb.c:1465:probe_access_flags: > assertion failed: (-(addr | TARGET_PAGE_MASK) >=3D size) > > Add the VSTART_CHECK_EARLY_EXIT() check for these helpers. > > This was found with a verification test generator based on RiESCUE. > > Reported-by: Nicholas Joaquin > Reported-by: Ganesh Valliappan > Signed-off-by: Nicholas Piggin Acked-by: Alistair Francis Alistair > --- > target/riscv/vector_helper.c | 2 + > tests/tcg/riscv64/Makefile.target | 5 ++ > tests/tcg/riscv64/test-vstart-overflow.c | 78 ++++++++++++++++++++++++ > 3 files changed, 85 insertions(+) > create mode 100644 tests/tcg/riscv64/test-vstart-overflow.c > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index caa8dd9c12..4126447d11 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -825,6 +825,8 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCV= State *env, uint32_t desc, > uint32_t esz =3D 1 << log2_esz; > int mmu_index =3D riscv_env_mmu_index(env, false); > > + VSTART_CHECK_EARLY_EXIT(env, evl); > + > /* Calculate the page range of first page */ > addr =3D base + (env->vstart << log2_esz); > page_split =3D -(addr | TARGET_PAGE_MASK); > diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefi= le.target > index 4da5b9a3b3..19a49b6467 100644 > --- a/tests/tcg/riscv64/Makefile.target > +++ b/tests/tcg/riscv64/Makefile.target > @@ -18,3 +18,8 @@ TESTS +=3D test-fcvtmod > test-fcvtmod: CFLAGS +=3D -march=3Drv64imafdc > test-fcvtmod: LDFLAGS +=3D -static > run-test-fcvtmod: QEMU_OPTS +=3D -cpu rv64,d=3Dtrue,zfa=3Dtrue > + > +# Test for vstart >=3D vl > +TESTS +=3D test-vstart-overflow > +test-vstart-overflow: CFLAGS +=3D -march=3Drv64gcv > +run-test-vstart-overflow: QEMU_OPTS +=3D -cpu rv64,v=3Don > diff --git a/tests/tcg/riscv64/test-vstart-overflow.c b/tests/tcg/riscv64= /test-vstart-overflow.c > new file mode 100644 > index 0000000000..6c904ab309 > --- /dev/null > +++ b/tests/tcg/riscv64/test-vstart-overflow.c > @@ -0,0 +1,78 @@ > +/* > + * Test for VSTART set to overflow VL > + * > + * TCG vector instructions should call VSTART_CHECK_EARLY_EXIT() to chec= k > + * this case, otherwise memory addresses can underflow and misbehave or > + * crash QEMU. > + * > + * TODO: Add stores and other instructions. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > +#include > + > +#define VSTART_OVERFLOW_TEST(insn) \ > +({ \ > + uint8_t vmem[64] =3D { 0 }; \ > + uint64_t vstart; \ > + asm volatile(" \r\n \ > + # Set VL=3D52 and VSTART=3D56 \r\n \ > + li t0, 52 \r\n \ > + vsetvli x0, t0, e8, m4, ta, ma \r\n \ > + li t0, 56 \r\n \ > + csrrw x0, vstart, t0 \r\n \ > + li t1, 64 \r\n \ > + " insn " \r\n \ > + csrr %0, vstart \r\n \ > + " : "=3Dr"(vstart), "+A"(vmem) :: "t0", "t1", "v24", "memory"); \ > + vstart; \ > +}) > + > +int run_vstart_overflow_tests() > +{ > + /* > + * An implementation is permitted to raise an illegal instruction > + * exception when executing a vector instruction if vstart is set to= a > + * value that could not be produced by the execution of that instruc= tion > + * with the same vtype. If TCG is changed to do this, then this test > + * could be updated to handle the SIGILL. > + */ > + if (VSTART_OVERFLOW_TEST("vl1re16.v v24, %1")) { > + return 1; > + } > + > + if (VSTART_OVERFLOW_TEST("vs1r.v v24, %1")) { > + return 1; > + } > + > + if (VSTART_OVERFLOW_TEST("vle16.v v24, %1")) { > + return 1; > + } > + > + if (VSTART_OVERFLOW_TEST("vse16.v v24, %1")) { > + return 1; > + } > + > + if (VSTART_OVERFLOW_TEST("vluxei8.v v24, %1, v20")) { > + return 1; > + } > + > + if (VSTART_OVERFLOW_TEST("vloxei8.v v24, %1, v20")) { > + return 1; > + } > + > + if (VSTART_OVERFLOW_TEST("vlse16.v v24, %1, t1")) { > + return 1; > + } > + > + if (VSTART_OVERFLOW_TEST("vlseg2e8.v v24, %1")) { > + return 1; > + } > + > + return 0; > +} > + > +int main() > +{ > + return run_vstart_overflow_tests(); > +} > -- > 2.51.0 > >