From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, palmer@dabbelt.com,
zhiwei_liu@linux.alibaba.com, fei2.wu@intel.com
Subject: Re: [PATCH v6 08/25] accel/tcg: Add cpu_ld*_code_mmu
Date: Tue, 11 Apr 2023 13:10:39 +1000 [thread overview]
Message-ID: <CAKmqyKP5AyhYrXncgmWVgjcz3WFwPPK6B+xauvqWV5hyrKszMQ@mail.gmail.com> (raw)
In-Reply-To: <20230325105429.1142530-9-richard.henderson@linaro.org>
On Sat, Mar 25, 2023 at 9:52 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> At least RISC-V has the need to be able to perform a read
> using execute permissions, outside of translation.
> Add helpers to facilitate this.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/exec/cpu_ldst.h | 9 +++++++
> accel/tcg/cputlb.c | 48 ++++++++++++++++++++++++++++++++++
> accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 115 insertions(+)
>
> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
> index 09b55cc0ee..c141f0394f 100644
> --- a/include/exec/cpu_ldst.h
> +++ b/include/exec/cpu_ldst.h
> @@ -445,6 +445,15 @@ static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
> # define cpu_stq_mmu cpu_stq_le_mmu
> #endif
>
> +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra);
> +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra);
> +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra);
> +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra);
> +
> uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
> uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
> uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index e984a98dc4..e62c8f3c3f 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -2768,3 +2768,51 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
> MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true));
> return full_ldq_code(env, addr, oi, 0);
> }
> +
> +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t retaddr)
> +{
> + return full_ldub_code(env, addr, oi, retaddr);
> +}
> +
> +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t retaddr)
> +{
> + MemOp mop = get_memop(oi);
> + int idx = get_mmuidx(oi);
> + uint16_t ret;
> +
> + ret = full_lduw_code(env, addr, make_memop_idx(MO_TEUW, idx), retaddr);
> + if ((mop & MO_BSWAP) != MO_TE) {
> + ret = bswap16(ret);
> + }
> + return ret;
> +}
> +
> +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t retaddr)
> +{
> + MemOp mop = get_memop(oi);
> + int idx = get_mmuidx(oi);
> + uint32_t ret;
> +
> + ret = full_ldl_code(env, addr, make_memop_idx(MO_TEUL, idx), retaddr);
> + if ((mop & MO_BSWAP) != MO_TE) {
> + ret = bswap32(ret);
> + }
> + return ret;
> +}
> +
> +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t retaddr)
> +{
> + MemOp mop = get_memop(oi);
> + int idx = get_mmuidx(oi);
> + uint64_t ret;
> +
> + ret = full_ldq_code(env, addr, make_memop_idx(MO_TEUQ, idx), retaddr);
> + if ((mop & MO_BSWAP) != MO_TE) {
> + ret = bswap64(ret);
> + }
> + return ret;
> +}
> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
> index 7b37fd229e..44e0ea55ba 100644
> --- a/accel/tcg/user-exec.c
> +++ b/accel/tcg/user-exec.c
> @@ -1222,6 +1222,64 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr)
> return ret;
> }
>
> +uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra)
> +{
> + void *haddr;
> + uint8_t ret;
> +
> + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH);
> + ret = ldub_p(haddr);
> + clear_helper_retaddr();
> + return ret;
> +}
> +
> +uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra)
> +{
> + void *haddr;
> + uint16_t ret;
> +
> + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH);
> + ret = lduw_p(haddr);
> + clear_helper_retaddr();
> + if (get_memop(oi) & MO_BSWAP) {
> + ret = bswap16(ret);
> + }
> + return ret;
> +}
> +
> +uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra)
> +{
> + void *haddr;
> + uint32_t ret;
> +
> + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH);
> + ret = ldl_p(haddr);
> + clear_helper_retaddr();
> + if (get_memop(oi) & MO_BSWAP) {
> + ret = bswap32(ret);
> + }
> + return ret;
> +}
> +
> +uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr,
> + MemOpIdx oi, uintptr_t ra)
> +{
> + void *haddr;
> + uint64_t ret;
> +
> + validate_memop(oi, MO_BEUQ);
> + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD);
> + ret = ldq_p(haddr);
> + clear_helper_retaddr();
> + if (get_memop(oi) & MO_BSWAP) {
> + ret = bswap64(ret);
> + }
> + return ret;
> +}
> +
> #include "ldst_common.c.inc"
>
> /*
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2023-04-11 3:11 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-25 10:54 [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups Richard Henderson
2023-03-25 10:54 ` [PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags Richard Henderson
2023-04-06 2:35 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 02/25] target/riscv: Add a general status enum for extensions Richard Henderson
2023-03-26 12:54 ` liweiwei
2023-04-11 2:05 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags Richard Henderson
2023-04-11 1:59 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Richard Henderson
2023-03-27 1:34 ` liweiwei
2023-03-27 16:22 ` Richard Henderson
2023-03-28 2:34 ` [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs,vs} " LIU Zhiwei
2023-04-11 2:02 ` [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} " Alistair Francis
2023-03-25 10:54 ` [PATCH v6 05/25] target/riscv: Add a tb flags field for vstart Richard Henderson
2023-04-11 2:07 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx Richard Henderson
2023-03-28 2:39 ` LIU Zhiwei
2023-04-11 2:08 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change Richard Henderson
2023-03-28 2:41 ` LIU Zhiwei
2023-04-11 2:11 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 08/25] accel/tcg: Add cpu_ld*_code_mmu Richard Henderson
2023-04-11 3:10 ` Alistair Francis [this message]
2023-03-25 10:54 ` [PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX Richard Henderson
2023-04-11 3:12 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers Richard Henderson
2023-04-11 3:34 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Richard Henderson
2023-04-11 3:36 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 12/25] target/riscv: Introduce mmuidx_sum Richard Henderson
2023-04-11 3:39 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 13/25] target/riscv: Introduce mmuidx_priv Richard Henderson
2023-03-27 2:07 ` LIU Zhiwei
2023-03-27 16:29 ` Richard Henderson
2023-03-28 1:33 ` LIU Zhiwei
2023-03-28 1:54 ` LIU Zhiwei
2023-03-28 14:27 ` Richard Henderson
2023-04-11 3:53 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage Richard Henderson
2023-04-11 3:55 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv Richard Henderson
2023-04-11 3:56 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Richard Henderson
2023-04-11 4:02 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 17/25] target/riscv: Check SUM in the correct register Richard Henderson
2023-04-11 4:25 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 18/25] target/riscv: Hoist second stage mode change to callers Richard Henderson
2023-04-11 4:25 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop Richard Henderson
2023-04-11 4:26 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 20/25] target/riscv: Move leaf pte processing out of " Richard Henderson
2023-04-11 4:30 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug Richard Henderson
2023-04-11 4:30 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 22/25] target/riscv: Don't modify SUM " Richard Henderson
2023-04-11 4:31 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags Richard Henderson
2023-04-11 4:32 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 24/25] target/riscv: Reorg access check in get_physical_address Richard Henderson
2023-04-11 4:55 ` Alistair Francis
2023-03-25 10:54 ` [PATCH v6 25/25] target/riscv: Reorg sum " Richard Henderson
2023-04-11 5:36 ` Alistair Francis
2023-03-26 5:17 ` [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups Richard Henderson
2023-03-26 14:18 ` liweiwei
2023-03-27 16:43 ` Daniel Henrique Barboza
2023-03-28 1:22 ` Wu, Fei
2023-04-04 6:42 ` Wu, Fei
2023-04-04 7:11 ` LIU Zhiwei
2023-04-04 7:23 ` Wu, Fei
2023-04-11 5:38 ` Alistair Francis
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