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Tue, 18 Jan 2022 19:21:45 -0800 (PST) MIME-Version: 1.0 References: <20220113114004.286796-1-zhiwei_liu@c-sky.com> <20220113114004.286796-4-zhiwei_liu@c-sky.com> In-Reply-To: <20220113114004.286796-4-zhiwei_liu@c-sky.com> From: Alistair Francis Date: Wed, 19 Jan 2022 13:21:19 +1000 Message-ID: Subject: Re: [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr To: LIU Zhiwei Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::d2c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::d2c; envelope-from=alistair23@gmail.com; helo=mail-io1-xd2c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, "open list:RISC-V" , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Palmer Dabbelt , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jan 13, 2022 at 9:45 PM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvi.c.inc | 4 +--- > target/riscv/translate.c | 4 +--- > 2 files changed, 2 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc > index 3a0ae28fef..b9ba57f266 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -68,9 +68,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) > tcg_temp_free(t0); > } > > - if (a->rd != 0) { > - tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn); > - } > + gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn); > tcg_gen_lookup_and_goto_ptr(); > > if (misaligned) { > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 615048ec87..b47b308920 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -367,10 +367,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) > return; > } > } > - if (rd != 0) { > - tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); > - } > > + gen_set_gpri(ctx, rd, ctx->pc_succ_insn); > gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ > ctx->base.is_jmp = DISAS_NORETURN; > } > -- > 2.25.1 > >