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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92a; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Sep 20, 2023 at 9:23=E2=80=AFPM Daniel Henrique Barboza wrote: > > We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next > patch and set_misa() needs to be usable from there. > > Rename it to riscv_cpu_set_misa() and make it public. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 34 ++++++++++++++++++---------------- > target/riscv/cpu.h | 1 + > 2 files changed, 19 insertions(+), 16 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 665c21af6a..cf191d576e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong caus= e, bool async) > } > } > > -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) > +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) > { > env->misa_mxl_max =3D env->misa_mxl =3D mxl; > env->misa_ext_mask =3D env->misa_ext =3D ext; > @@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj) > RISCVCPU *cpu =3D RISCV_CPU(obj); > CPURISCVState *env =3D &cpu->env; > #if defined(TARGET_RISCV32) > - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC = | RVU); > #elif defined(TARGET_RISCV64) > - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC = | RVU); > #endif > > #ifndef CONFIG_USER_ONLY > @@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj) > #ifdef TARGET_RISCV32 > mlx =3D MXL_RV32; > #endif > - set_misa(env, mlx, 0); > + riscv_cpu_set_misa(env, mlx, 0); > env->priv_ver =3D PRIV_VERSION_LATEST; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? > @@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj) > { > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > - set_misa(env, MXL_RV64, 0); > + riscv_cpu_set_misa(env, MXL_RV64, 0); > /* Set latest version of privileged specification */ > env->priv_ver =3D PRIV_VERSION_LATEST; > #ifndef CONFIG_USER_ONLY > @@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj) > { > RISCVCPU *cpu =3D RISCV_CPU(obj); > CPURISCVState *env =3D &cpu->env; > - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RV= U); > + riscv_cpu_set_misa(env, MXL_RV64, > + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > env->priv_ver =3D PRIV_VERSION_1_10_0; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); > @@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > RISCVCPU *cpu =3D RISCV_CPU(obj); > > - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > env->priv_ver =3D PRIV_VERSION_1_10_0; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > @@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > RISCVCPU *cpu =3D RISCV_CPU(obj); > > - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); > + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); > env->priv_ver =3D PRIV_VERSION_1_11_0; > > cpu->cfg.ext_zfa =3D true; > @@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > RISCVCPU *cpu =3D RISCV_CPU(obj); > > - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); > + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); > env->priv_ver =3D PRIV_VERSION_1_12_0; > > /* Enable ISA extensions */ > @@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj) > } > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > - set_misa(env, MXL_RV128, 0); > + riscv_cpu_set_misa(env, MXL_RV128, 0); > /* Set latest version of privileged specification */ > env->priv_ver =3D PRIV_VERSION_LATEST; > #ifndef CONFIG_USER_ONLY > @@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj) > { > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > - set_misa(env, MXL_RV32, 0); > + riscv_cpu_set_misa(env, MXL_RV32, 0); > /* Set latest version of privileged specification */ > env->priv_ver =3D PRIV_VERSION_LATEST; > #ifndef CONFIG_USER_ONLY > @@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj) > { > RISCVCPU *cpu =3D RISCV_CPU(obj); > CPURISCVState *env =3D &cpu->env; > - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RV= U); > + riscv_cpu_set_misa(env, MXL_RV32, > + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > env->priv_ver =3D PRIV_VERSION_1_10_0; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); > @@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > RISCVCPU *cpu =3D RISCV_CPU(obj); > > - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > env->priv_ver =3D PRIV_VERSION_1_10_0; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > @@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj) > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > RISCVCPU *cpu =3D RISCV_CPU(obj); > > - set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > env->priv_ver =3D PRIV_VERSION_1_11_0; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > @@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > CPURISCVState *env =3D &RISCV_CPU(obj)->env; > RISCVCPU *cpu =3D RISCV_CPU(obj); > > - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU)= ; > env->priv_ver =3D PRIV_VERSION_1_10_0; > #ifndef CONFIG_USER_ONLY > set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > @@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *o= bj) > const RISCVCPUMultiExtConfig *prop; > > /* Enable RVG, RVJ and RVV that are disabled by default */ > - set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); > + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | R= VV); > > for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { > isa_ext_update_enabled(cpu, prop->offset, true); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7235eafc1a..9ec0805596 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t e= xt_offset, bool en); > bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); > bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); > int cpu_cfg_ext_get_min_version(uint32_t ext_offset); > +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); > void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); > > typedef struct RISCVCPUMultiExtConfig { > -- > 2.41.0 > >