From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Zhanghailiang <zhang.zhanghailiang@huawei.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"Zhangxiaofeng \(F\)" <victor.zhangxiaofeng@huawei.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
yinyipeng <yinyipeng1@huawei.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Wubin \(H\)" <wu.wubin@huawei.com>,
"dengkai \(A\)" <dengkai1@huawei.com>
Subject: Re: [PATCH V3 4/6] target/riscv: Add H extension state description
Date: Fri, 23 Oct 2020 17:00:17 -0700 [thread overview]
Message-ID: <CAKmqyKP8mMV6_Qb-twgheB6rbW2e_vv9tBYFi3tX8qGPMjnxXQ@mail.gmail.com> (raw)
In-Reply-To: <20201023091225.224-5-jiangyifei@huawei.com>
On Fri, Oct 23, 2020 at 2:16 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> In the case of supporting H extension, add H extension description
> to vmstate_riscv_cpu.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/machine.c | 47 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index fc1461d88e..ae60050898 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -68,6 +68,52 @@ static const VMStateDescription vmstate_pmp = {
> }
> };
>
> +static bool hyper_needed(void *opaque)
> +{
> + RISCVCPU *cpu = opaque;
> + CPURISCVState *env = &cpu->env;
> +
> + return riscv_has_ext(env, RVH);
> +}
> +
> +static const VMStateDescription vmstate_hyper = {
> + .name = "cpu/hyper",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .needed = hyper_needed,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINTTL(env.hstatus, RISCVCPU),
> + VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
> + VMSTATE_UINTTL(env.hideleg, RISCVCPU),
> + VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
> + VMSTATE_UINTTL(env.htval, RISCVCPU),
> + VMSTATE_UINTTL(env.htinst, RISCVCPU),
> + VMSTATE_UINTTL(env.hgatp, RISCVCPU),
> + VMSTATE_UINT64(env.htimedelta, RISCVCPU),
> +
> + VMSTATE_UINT64(env.vsstatus, RISCVCPU),
> + VMSTATE_UINTTL(env.vstvec, RISCVCPU),
> + VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
> + VMSTATE_UINTTL(env.vsepc, RISCVCPU),
> + VMSTATE_UINTTL(env.vscause, RISCVCPU),
> + VMSTATE_UINTTL(env.vstval, RISCVCPU),
> + VMSTATE_UINTTL(env.vsatp, RISCVCPU),
> +
> + VMSTATE_UINTTL(env.mtval2, RISCVCPU),
> + VMSTATE_UINTTL(env.mtinst, RISCVCPU),
> +
> + VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
> + VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
> + VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
> +
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> .version_id = 1,
> @@ -119,6 +165,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> },
> .subsections = (const VMStateDescription * []) {
> &vmstate_pmp,
> + &vmstate_hyper,
> NULL
> }
> };
> --
> 2.19.1
>
>
next prev parent reply other threads:[~2020-10-24 0:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 9:12 [PATCH V3 0/6] Support RISC-V migration Yifei Jiang
2020-10-23 9:12 ` [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Yifei Jiang
2020-10-23 9:41 ` Jiangyifei
2020-10-23 23:50 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 2/6] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-23 23:52 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 3/6] target/riscv: Add PMP state description Yifei Jiang
2020-10-23 23:59 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 4/6] target/riscv: Add H extension " Yifei Jiang
2020-10-24 0:00 ` Alistair Francis [this message]
2020-10-23 9:12 ` [PATCH V3 5/6] target/riscv: Add V " Yifei Jiang
2020-10-24 0:01 ` Alistair Francis
2020-10-23 9:12 ` [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate Yifei Jiang
2020-10-24 0:02 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAKmqyKP8mMV6_Qb-twgheB6rbW2e_vv9tBYFi3tX8qGPMjnxXQ@mail.gmail.com \
--to=alistair23@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=dengkai1@huawei.com \
--cc=jiangyifei@huawei.com \
--cc=kbastian@mail.uni-paderborn.de \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=sagark@eecs.berkeley.edu \
--cc=victor.zhangxiaofeng@huawei.com \
--cc=wu.wubin@huawei.com \
--cc=yinyipeng1@huawei.com \
--cc=zhang.zhanghailiang@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).