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From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns
Date: Tue, 18 Jan 2022 08:27:20 +1000	[thread overview]
Message-ID: <CAKmqyKPCCAzjkNGPe3E9etbKPzG3KS24eaqbo0nAjP7RpGaUJA@mail.gmail.com> (raw)
In-Reply-To: <20211229023348.12606-4-frank.chang@sifive.com>

On Wed, Dec 29, 2021 at 12:34 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++++++++++----
>  1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5b47729a21..820a3387db 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
>                                  uint8_t eew)
>  {
>      int8_t emul = eew - s->sew + s->lmul;
> -    return (emul >= -3 && emul <= 3) &&
> -            require_align(vs2, emul) &&
> -            require_align(vd, s->lmul) &&
> -            require_nf(vd, nf, s->lmul);
> +    bool ret = (emul >= -3 && emul <= 3) &&
> +               require_align(vs2, emul) &&
> +               require_align(vd, s->lmul) &&
> +               require_nf(vd, nf, s->lmul);
> +#ifdef TARGET_RISCV32

Don't use hardcoded macros for this, instead use get_xl()

Alistair

> +    /*
> +     * All Zve* extensions support all vector load and store instructions,
> +     * except Zve64* extensions do not support EEW=64 for index values
> +     * when XLEN=32. (Section 18.2)
> +     */
> +    ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
> +#endif
> +    return ret;
>  }
>
>  /*
> --
> 2.31.1
>
>


  reply	other threads:[~2022-01-17 22:32 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-29  2:33 [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions frank.chang
2021-12-29  2:33 ` [PATCH 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V frank.chang
2022-01-17 22:23   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns frank.chang
2022-01-17 22:21   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns frank.chang
2022-01-17 22:27   ` Alistair Francis [this message]
2022-01-18  1:37     ` Frank Chang
2021-12-29  2:33 ` [PATCH 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns frank.chang
2022-01-17 22:30   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns frank.chang
2022-01-17 22:31   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns frank.chang
2022-01-17 22:39   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns frank.chang
2022-01-17 22:50   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns frank.chang
2022-01-17 22:51   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing " frank.chang
2022-01-17 22:53   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on frank.chang
2022-01-17 22:53   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V frank.chang
2022-01-17 22:54   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns frank.chang
2022-01-17 22:54   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns frank.chang
2022-01-17 22:55   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns frank.chang
2022-01-17 22:56   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns frank.chang
2022-01-17 22:56   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing " frank.chang
2022-01-17 22:57   ` Alistair Francis
2021-12-29  2:33 ` [PATCH 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on frank.chang
2022-01-17 22:57   ` Alistair Francis
2022-01-17 12:55 ` [PATCH 00/17] Add RISC-V RVV Zve32f and Zve64f extensions Frank Chang

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