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Mon, 17 Jan 2022 14:27:46 -0800 (PST) MIME-Version: 1.0 References: <20211229023348.12606-1-frank.chang@sifive.com> <20211229023348.12606-4-frank.chang@sifive.com> In-Reply-To: <20211229023348.12606-4-frank.chang@sifive.com> From: Alistair Francis Date: Tue, 18 Jan 2022 08:27:20 +1000 Message-ID: Subject: Re: [PATCH 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns To: Frank Chang Content-Type: text/plain; charset="UTF-8" X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::d2e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::d2e; envelope-from=alistair23@gmail.com; helo=mail-io1-xd2e.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Palmer Dabbelt , Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Dec 29, 2021 at 12:34 PM wrote: > > From: Frank Chang > > All Zve* extensions support all vector load and store instructions, > except Zve64* extensions do not support EEW=64 for index values when > XLEN=32. > > Signed-off-by: Frank Chang > --- > target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 5b47729a21..820a3387db 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, > uint8_t eew) > { > int8_t emul = eew - s->sew + s->lmul; > - return (emul >= -3 && emul <= 3) && > - require_align(vs2, emul) && > - require_align(vd, s->lmul) && > - require_nf(vd, nf, s->lmul); > + bool ret = (emul >= -3 && emul <= 3) && > + require_align(vs2, emul) && > + require_align(vd, s->lmul) && > + require_nf(vd, nf, s->lmul); > +#ifdef TARGET_RISCV32 Don't use hardcoded macros for this, instead use get_xl() Alistair > + /* > + * All Zve* extensions support all vector load and store instructions, > + * except Zve64* extensions do not support EEW=64 for index values > + * when XLEN=32. (Section 18.2) > + */ > + ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true); > +#endif > + return ret; > } > > /* > -- > 2.31.1 > >