From: Alistair Francis <alistair23@gmail.com>
To: Anton Johansson <anjo@rev.ng>
Cc: qemu-devel@nongnu.org, pierrick.bouvier@linaro.org,
philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com
Subject: Re: [PATCH v4 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry()
Date: Fri, 31 Oct 2025 12:53:59 +1000 [thread overview]
Message-ID: <CAKmqyKPKNhW5ux0OMXaURQCyYeCjf76dQAozS_1WTvFG-fddXQ@mail.gmail.com> (raw)
In-Reply-To: <20251027181831.27016-28-anjo@rev.ng>
On Tue, Oct 28, 2025 at 4:24 AM Anton Johansson via
<qemu-devel@nongnu.org> wrote:
>
> Widen to 64 bits in size to hold all relevant values. Note: src and dst
> arguments change from signed to unsigned but no functional change is
> incurred.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 5 +++--
> target/riscv/cpu_helper.c | 5 +++--
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c2be30795a..ee4444f22d 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -662,8 +662,9 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
> void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv,
> bool virt_en);
>
> -void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
> - enum CTRType type, privilege_mode_t prev_priv, bool prev_virt);
> +void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst,
> + enum CTRType type, privilege_mode_t prev_priv,
> + bool prev_virt);
> void riscv_ctr_clear(CPURISCVState *env);
>
> void riscv_translate_init(void);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index b102f15ac6..20ff05a4b2 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -926,8 +926,9 @@ static bool riscv_ctr_check_xte(CPURISCVState *env,
> * entry = isel - CTR_ENTRIES_FIRST;
> * idx = (sctrstatus.WRPTR - entry - 1) & (depth - 1);
> */
> -void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
> - enum CTRType type, privilege_mode_t src_priv, bool src_virt)
> +void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst,
> + enum CTRType type, privilege_mode_t src_priv,
> + bool src_virt)
> {
> bool tgt_virt = env->virt_enabled;
> uint64_t src_mask = riscv_ctr_priv_to_mask(src_priv, src_virt);
> --
> 2.51.0
>
>
next prev parent reply other threads:[~2025-10-31 2:55 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 18:17 [PATCH v4 00/33] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-27 18:17 ` [PATCH v4 01/33] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-27 18:17 ` [PATCH v4 02/33] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 03/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-31 1:32 ` Alistair Francis
2025-10-31 13:05 ` Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 04/33] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 05/33] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-28 8:14 ` Pierrick Bouvier
2025-10-27 18:18 ` [PATCH v4 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 07/33] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 09/33] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-28 8:15 ` Pierrick Bouvier
2025-10-27 18:18 ` [PATCH v4 10/33] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-31 1:56 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 11/33] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 12/33] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 13/33] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 14/33] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 15/33] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 16/33] target/riscv: Fix size of retxh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 17/33] target/riscv: Fix size of ssp Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 18/33] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-31 1:57 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 19/33] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 20/33] target/riscv: Fix size of priv Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 21/33] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 22/33] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-31 1:59 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-31 2:51 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 24/33] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-31 2:52 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 25/33] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis [this message]
2025-10-27 18:18 ` [PATCH v4 28/33] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-31 2:54 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 29/33] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-31 2:55 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 30/33] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 31/33] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 32/33] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 33/33] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
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