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Wed, 18 Aug 2021 23:29:13 -0700 (PDT) MIME-Version: 1.0 References: <20210817211803.283639-1-richard.henderson@linaro.org> <20210817211803.283639-7-richard.henderson@linaro.org> In-Reply-To: <20210817211803.283639-7-richard.henderson@linaro.org> From: Alistair Francis Date: Thu, 19 Aug 2021 16:28:47 +1000 Message-ID: Subject: Re: [PATCH v2 06/21] target/riscv: Remove gen_arith_div* To: Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d2d; envelope-from=alistair23@gmail.com; helo=mail-io1-xd2d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Bin Meng , Alistair Francis , "qemu-devel@nongnu.org Developers" , liuzhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Aug 18, 2021 at 7:21 AM Richard Henderson wrote: > > Use ctx->w and the enhanced gen_arith function. > > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c | 42 ------------------------- > target/riscv/insn_trans/trans_rvm.c.inc | 16 +++++----- > 2 files changed, 8 insertions(+), 50 deletions(-) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 4819682bf1..e337dca01b 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -491,48 +491,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, > return true; > } > > -static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, > - void(*func)(TCGv, TCGv, TCGv)) > -{ > - TCGv source1, source2; > - source1 = tcg_temp_new(); > - source2 = tcg_temp_new(); > - > - gen_get_gpr(ctx, source1, a->rs1); > - gen_get_gpr(ctx, source2, a->rs2); > - tcg_gen_ext32s_tl(source1, source1); > - tcg_gen_ext32s_tl(source2, source2); > - > - (*func)(source1, source1, source2); > - > - tcg_gen_ext32s_tl(source1, source1); > - gen_set_gpr(ctx, a->rd, source1); > - tcg_temp_free(source1); > - tcg_temp_free(source2); > - return true; > -} > - > -static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, > - void(*func)(TCGv, TCGv, TCGv)) > -{ > - TCGv source1, source2; > - source1 = tcg_temp_new(); > - source2 = tcg_temp_new(); > - > - gen_get_gpr(ctx, source1, a->rs1); > - gen_get_gpr(ctx, source2, a->rs2); > - tcg_gen_ext32u_tl(source1, source1); > - tcg_gen_ext32u_tl(source2, source2); > - > - (*func)(source1, source1, source2); > - > - tcg_gen_ext32s_tl(source1, source1); > - gen_set_gpr(ctx, a->rd, source1); > - tcg_temp_free(source1); > - tcg_temp_free(source2); > - return true; > -} > - > static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) > { > tcg_gen_deposit_tl(ret, arg1, arg2, > diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc > index 013b3f7009..3d93b24c25 100644 > --- a/target/riscv/insn_trans/trans_rvm.c.inc > +++ b/target/riscv/insn_trans/trans_rvm.c.inc > @@ -99,30 +99,30 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_EXT(ctx, RVM); > - > - return gen_arith_div_w(ctx, a, &gen_div); > + ctx->w = true; > + return gen_arith(ctx, a, EXT_SIGN, gen_div); > } > > static bool trans_divuw(DisasContext *ctx, arg_divuw *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_EXT(ctx, RVM); > - > - return gen_arith_div_uw(ctx, a, &gen_divu); > + ctx->w = true; > + return gen_arith(ctx, a, EXT_ZERO, gen_divu); > } > > static bool trans_remw(DisasContext *ctx, arg_remw *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_EXT(ctx, RVM); > - > - return gen_arith_div_w(ctx, a, &gen_rem); > + ctx->w = true; > + return gen_arith(ctx, a, EXT_SIGN, gen_rem); > } > > static bool trans_remuw(DisasContext *ctx, arg_remuw *a) > { > REQUIRE_64BIT(ctx); > REQUIRE_EXT(ctx, RVM); > - > - return gen_arith_div_uw(ctx, a, &gen_remu); > + ctx->w = true; > + return gen_arith(ctx, a, EXT_ZERO, gen_remu); > } > -- > 2.25.1 > >