qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: Atish Patra <atish.patra@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
Date: Wed, 3 Nov 2021 15:40:16 +1000	[thread overview]
Message-ID: <CAKmqyKPOu2nDE8DEMSV55mp7UCYcsS45Y9dDCbeKXvEh6HxDbw@mail.gmail.com> (raw)
In-Reply-To: <20211025195601.245631-2-atish.patra@wdc.com>

On Tue, Oct 26, 2021 at 6:39 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The predicate function calculates the counter index incorrectly for
> hpmcounterx. Fix the counter index to reflect correct CSR number.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 23fbbd32162a..1ec776013435 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -89,8 +89,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>              }
>              break;
>          case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
> -            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
> -                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
> +            ctr_index = csrno - CSR_CYCLE;
> +            if (!get_field(env->hcounteren, 1 << ctr_index) &&
> +                 get_field(env->mcounteren, 1 << ctr_index)) {
>                  return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>              }
>              break;
> @@ -116,8 +117,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
>                  }
>                  break;
>              case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
> -                if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
> -                    get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
> +                ctr_index = csrno - CSR_CYCLEH;
> +                if (!get_field(env->hcounteren, 1 << ctr_index) &&
> +                     get_field(env->mcounteren, 1 << ctr_index)) {
>                      return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
>                  }
>                  break;
> --
> 2.31.1
>
>


  reply	other threads:[~2021-11-03  5:45 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-25 19:55 [ PATCH v3 00/10] Improve PMU support Atish Patra
2021-10-25 19:55 ` [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function Atish Patra
2021-11-03  5:40   ` Alistair Francis [this message]
2021-11-04 11:00   ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for Atish Patra
2021-11-03  5:43   ` Alistair Francis
2021-11-04 11:07   ` Bin Meng
2022-01-05 21:46     ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2021-11-03  5:47   ` Alistair Francis
2021-11-04 11:10   ` Bin Meng
2022-01-05 21:48     ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable Atish Patra
2021-11-03  5:50   ` Alistair Francis
2021-11-04 11:45   ` Bin Meng
2022-01-05 21:51     ` Atish Patra
2021-10-25 19:55 ` [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR Atish Patra
2021-11-03  5:51   ` Alistair Francis
2021-11-04 11:49   ` Bin Meng
2021-10-25 19:55 ` [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2021-10-25 19:55 ` [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation Atish Patra
2021-10-25 19:55 ` [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support Atish Patra
2021-12-27  4:37   ` Frank Chang
2022-01-07  0:38     ` Atish Patra
2021-10-25 19:56 ` [ PATCH v3 09/10] target/riscv: Add few cache related PMU events Atish Patra
2021-10-25 19:56 ` [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKmqyKPOu2nDE8DEMSV55mp7UCYcsS45Y9dDCbeKXvEh6HxDbw@mail.gmail.com \
    --to=alistair23@gmail.com \
    --cc=alistair.francis@wdc.com \
    --cc=atish.patra@wdc.com \
    --cc=bin.meng@windriver.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).