From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH 4/8] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize()
Date: Fri, 11 Aug 2023 10:52:24 -0400 [thread overview]
Message-ID: <CAKmqyKPSC1_oT6muzGtFs-sU2Vbrg0K9Vs_QT+661BSrBe09Kg@mail.gmail.com> (raw)
In-Reply-To: <20230728131520.110394-5-dbarboza@ventanamicro.com>
On Fri, Jul 28, 2023 at 10:08 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Let's change the other instances in realize() where we're enabling an
> extension based on a certain criteria (e.g. it's a dependency of another
> extension).
>
> We're leaving icsr and ifencei being enabled during RVG for later -
> we'll want to error out in that case. Every other extension enablement
> during realize is now done via cpu_cfg_ext_auto_update().
>
> The end goal is that only cpu init() functions will handle extension
> flags directly via "cpu->cfg.ext_N = true|false".
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 50 +++++++++++++++++++++++-----------------------
> 1 file changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 75dc83407e..88b263e830 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1174,7 +1174,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> }
>
> if (cpu->cfg.ext_zfh) {
> - cpu->cfg.ext_zfhmin = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
> }
>
> if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
> @@ -1200,17 +1200,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> }
>
> /* The V vector extension depends on the Zve64d extension */
> - cpu->cfg.ext_zve64d = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
> }
>
> /* The Zve64d extension depends on the Zve64f extension */
> if (cpu->cfg.ext_zve64d) {
> - cpu->cfg.ext_zve64f = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
> }
>
> /* The Zve64f extension depends on the Zve32f extension */
> if (cpu->cfg.ext_zve64f) {
> - cpu->cfg.ext_zve32f = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
> }
>
> if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
> @@ -1224,7 +1224,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> }
>
> if (cpu->cfg.ext_zvfh) {
> - cpu->cfg.ext_zvfhmin = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
> }
>
> if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
> @@ -1254,7 +1254,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>
> /* Set the ISA extensions, checks should have happened above */
> if (cpu->cfg.ext_zhinx) {
> - cpu->cfg.ext_zhinxmin = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> }
>
> if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
> @@ -1275,12 +1275,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> }
>
> if (cpu->cfg.ext_zce) {
> - cpu->cfg.ext_zca = true;
> - cpu->cfg.ext_zcb = true;
> - cpu->cfg.ext_zcmp = true;
> - cpu->cfg.ext_zcmt = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
> if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
> - cpu->cfg.ext_zcf = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> }
> }
>
> @@ -1329,26 +1329,26 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> }
>
> if (cpu->cfg.ext_zk) {
> - cpu->cfg.ext_zkn = true;
> - cpu->cfg.ext_zkr = true;
> - cpu->cfg.ext_zkt = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
> }
>
> if (cpu->cfg.ext_zkn) {
> - cpu->cfg.ext_zbkb = true;
> - cpu->cfg.ext_zbkc = true;
> - cpu->cfg.ext_zbkx = true;
> - cpu->cfg.ext_zkne = true;
> - cpu->cfg.ext_zknd = true;
> - cpu->cfg.ext_zknh = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
> }
>
> if (cpu->cfg.ext_zks) {
> - cpu->cfg.ext_zbkb = true;
> - cpu->cfg.ext_zbkc = true;
> - cpu->cfg.ext_zbkx = true;
> - cpu->cfg.ext_zksed = true;
> - cpu->cfg.ext_zksh = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
> }
>
> /*
> --
> 2.41.0
>
>
next prev parent reply other threads:[~2023-08-11 14:53 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-28 13:15 [PATCH 0/8] riscv: detecting user choice in TCG extensions Daniel Henrique Barboza
2023-07-28 13:15 ` [PATCH 1/8] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Daniel Henrique Barboza
2023-08-10 17:30 ` Alistair Francis
2023-07-28 13:15 ` [PATCH 2/8] target/riscv: make CPUCFG() macro public Daniel Henrique Barboza
2023-08-10 17:31 ` Alistair Francis
2023-07-28 13:15 ` [PATCH 3/8] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-08-11 14:50 ` Alistair Francis
2023-07-28 13:15 ` [PATCH 4/8] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Daniel Henrique Barboza
2023-08-11 14:52 ` Alistair Francis [this message]
2023-07-28 13:15 ` [PATCH 5/8] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Daniel Henrique Barboza
2023-08-11 15:03 ` Alistair Francis
2023-07-28 13:15 ` [PATCH 6/8] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Daniel Henrique Barboza
2023-08-11 15:04 ` Alistair Francis
2023-07-28 13:15 ` [PATCH 7/8] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-08-11 15:04 ` Alistair Francis
2023-07-28 13:15 ` [PATCH 8/8] target/riscv/cpu.c: consider user option with RVG Daniel Henrique Barboza
2023-08-11 15:05 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAKmqyKPSC1_oT6muzGtFs-sU2Vbrg0K9Vs_QT+661BSrBe09Kg@mail.gmail.com \
--to=alistair23@gmail.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).