Re: [PATCH] hw/riscv: sifive_u: Add a dummy L2 cache controller device

[Alistair Francis <alistair23@gmail.com>]

On Sun, Jul 19, 2020 at 11:50 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> It is enough to simply map the SiFive FU540 L2 cache controller
> into the MMIO space using create_unimplemented_device(), with an
> FDT fragment generated, to make the latest upstream U-Boot happy.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Applied to riscv-to-apply.next tree for 5.2.

Alistair

> ---
>
>  hw/riscv/sifive_u.c         | 22 ++++++++++++++++++++++
>  include/hw/riscv/sifive_u.h |  4 ++++
>  2 files changed, 26 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 6487d5e..f771cb0 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -72,6 +72,7 @@ static const struct MemmapEntry {
>      [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
>      [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
>      [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
> +    [SIFIVE_U_L2CC] =     {  0x2010000,     0x1000 },
>      [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
>      [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
>      [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
> @@ -302,6 +303,24 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
>      qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
>      g_free(nodename);
>
> +    nodename = g_strdup_printf("/soc/cache-controller@%lx",
> +        (long)memmap[SIFIVE_U_L2CC].base);
> +    qemu_fdt_add_subnode(fdt, nodename);
> +    qemu_fdt_setprop_cells(fdt, nodename, "reg",
> +        0x0, memmap[SIFIVE_U_L2CC].base,
> +        0x0, memmap[SIFIVE_U_L2CC].size);
> +    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
> +        SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
> +    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> +    qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
> +    qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
> +    qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
> +    qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
> +    qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
> +    qemu_fdt_setprop_string(fdt, nodename, "compatible",
> +                            "sifive,fu540-c000-ccache");
> +    g_free(nodename);
> +
>      phy_phandle = phandle++;
>      nodename = g_strdup_printf("/soc/ethernet@%lx",
>          (long)memmap[SIFIVE_U_GEM].base);
> @@ -732,6 +751,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
>      create_unimplemented_device("riscv.sifive.u.dmc",
>          memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
> +
> +    create_unimplemented_device("riscv.sifive.u.l2cc",
> +        memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
>  }
>
>  static Property sifive_u_soc_props[] = {
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index aba4d01..d3c0c00 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -71,6 +71,7 @@ enum {
>      SIFIVE_U_DEBUG,
>      SIFIVE_U_MROM,
>      SIFIVE_U_CLINT,
> +    SIFIVE_U_L2CC,
>      SIFIVE_U_L2LIM,
>      SIFIVE_U_PLIC,
>      SIFIVE_U_PRCI,
> @@ -86,6 +87,9 @@ enum {
>  };
>
>  enum {
> +    SIFIVE_U_L2CC_IRQ0 = 1,
> +    SIFIVE_U_L2CC_IRQ1 = 2,
> +    SIFIVE_U_L2CC_IRQ2 = 3,
>      SIFIVE_U_UART0_IRQ = 4,
>      SIFIVE_U_UART1_IRQ = 5,
>      SIFIVE_U_GPIO_IRQ0 = 7,
> --
> 2.7.4
>
>