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Mon, 16 May 2022 18:37:38 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Alistair Francis Date: Tue, 17 May 2022 11:37:11 +1000 Message-ID: Subject: Re: [PATCH v2 5/5] target/riscv: Move/refactor ISA extension checks To: Tsukasa OI Cc: Frank Chang , "qemu-devel@nongnu.org Developers" , "open list:RISC-V" Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::d33; envelope-from=alistair23@gmail.com; helo=mail-io1-xd33.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, May 15, 2022 at 12:56 PM Tsukasa OI wrote: > > We should separate "check" and "configure" steps as possible. > This commit separates both steps except vector/Zfinx-related checks. > > Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 31 ++++++++++++++++--------------- > 1 file changed, 16 insertions(+), 15 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f910a41407..5ab246bf63 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -630,14 +630,27 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { > + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); > + return; > + } > + > + /* Set the ISA extensions, checks should have happened above */ > if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || > cpu->cfg.ext_zhinxmin) { > cpu->cfg.ext_zfinx = true; > } > > - if (cpu->cfg.ext_zfinx && !cpu->cfg.ext_icsr) { > - error_setg(errp, "Zfinx extension requires Zicsr"); > - return; > + if (cpu->cfg.ext_zfinx) { > + if (!cpu->cfg.ext_icsr) { > + error_setg(errp, "Zfinx extension requires Zicsr"); > + return; > + } > + if (cpu->cfg.ext_f) { > + error_setg(errp, > + "Zfinx cannot be supported together with F extension"); > + return; > + } > } > > if (cpu->cfg.ext_zk) { > @@ -663,7 +676,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > cpu->cfg.ext_zksh = true; > } > > - /* Set the ISA extensions, checks should have happened above */ > if (cpu->cfg.ext_i) { > ext |= RVI; > } > @@ -734,20 +746,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > set_vext_version(env, vext_version); > } > - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { > - error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); > - return; > - } > if (cpu->cfg.ext_j) { > ext |= RVJ; > } > - if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh || > - cpu->cfg.ext_zfhmin)) { > - error_setg(errp, > - "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh'," > - " 'Zfhmin'"); > - return; > - } > > set_misa(env, env->misa_mxl, ext); > } > -- > 2.34.1 >