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Wed, 25 Mar 2026 19:09:54 -0700 (PDT) MIME-Version: 1.0 References: <20260318103122.97244-1-philmd@linaro.org> <20260318103122.97244-8-philmd@linaro.org> In-Reply-To: <20260318103122.97244-8-philmd@linaro.org> From: Alistair Francis Date: Thu, 26 Mar 2026 12:09:28 +1000 X-Gm-Features: AQROBzB_T7P1nV4hIeuIgaPA5afWcrG_7nfmKusiWXzI6DE10j-HccBTICG9wk8 Message-ID: Subject: Re: [PATCH-for-11.1 07/16] target/riscv: Factor tiny ldn() helper in gdbstub To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Weiwei Li , Pierrick Bouvier , Warner Losh , =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , Vijai Kumar K , Anton Johansson , Daniel Henrique Barboza , qemu-riscv@nongnu.org, Alistair Francis , Palmer Dabbelt , Jiaxun Yang , Peter Maydell , Liu Zhiwei , Djordje Todorovic Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Mar 18, 2026 at 8:33=E2=80=AFPM Philippe Mathieu-Daud=C3=A9 wrote: > > In preparation of having this helper handle CPU runtime > endianness changes, factor the ldn() helper out. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > target/riscv/gdbstub.c | 22 +++++++++++++--------- > 1 file changed, 13 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index 6a5b7a82fd4..be42566bcc8 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -47,6 +47,11 @@ static const struct TypeSize vec_lanes[] =3D { > { "uint8", "bytes", 8, 'b' }, > }; > > +static uint64_t ldn(CPURISCVState *env, uint8_t *mem_buf, size_t regsz) > +{ > + return ldn_p(mem_buf, regsz); > +} > + > int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n= ) > { > RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); > @@ -84,15 +89,15 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_= t *mem_buf, int n) > > switch (mcc->def->misa_mxl_max) { > case MXL_RV32: > - tmp =3D (int32_t)ldl_p(mem_buf); > + tmp =3D (int32_t)ldn(env, mem_buf, 4); > length =3D 4; > break; > case MXL_RV64: > case MXL_RV128: > if (env->xl < MXL_RV64) { > - tmp =3D (int32_t)ldq_p(mem_buf); > + tmp =3D (int32_t)ldn(env, mem_buf, 8); > } else { > - tmp =3D ldq_p(mem_buf); > + tmp =3D ldn(env, mem_buf, 8); > } > length =3D 8; > break; > @@ -130,7 +135,7 @@ static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *m= em_buf, int n) > CPURISCVState *env =3D &cpu->env; > > if (n < 32) { > - env->fpr[n] =3D ldq_p(mem_buf); /* always 64-bit */ > + env->fpr[n] =3D ldn(env, mem_buf, 8); /* always 64-bit */ > return sizeof(uint64_t); > } > return 0; > @@ -162,7 +167,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t= *mem_buf, int n) > if (n < 32) { > int i; > for (i =3D 0; i < vlenb; i +=3D 8) { > - env->vreg[(n * vlenb + i) / 8] =3D ldq_p(mem_buf + i); > + env->vreg[(n * vlenb + i) / 8] =3D ldn(env, mem_buf + i, 8); > } > return vlenb; > } > @@ -194,7 +199,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *m= em_buf, int n) > const unsigned regsz =3D riscv_cpu_is_32bit(cpu) ? 4 : 8; > > if (n < CSR_TABLE_SIZE) { > - uint64_t val =3D ldn_p(mem_buf, regsz); > + uint64_t val =3D ldn(env, mem_buf, regsz); > int result; > > result =3D riscv_csrrw_debug(env, n, NULL, val, -1); > @@ -230,8 +235,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_= t *mem_buf, int n) > const unsigned regsz =3D riscv_cpu_is_32bit(cpu) ? 4 : 8; > #ifndef CONFIG_USER_ONLY > CPURISCVState *env =3D &cpu->env; > - > - target_ulong new_priv =3D ldn_p(mem_buf, regsz) & 0x3; > + uint64_t new_priv =3D ldn(env, mem_buf, regsz) & 0x3; > bool new_virt =3D 0; > > if (new_priv =3D=3D PRV_RESERVED) { > @@ -239,7 +243,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_= t *mem_buf, int n) > } > > if (new_priv !=3D PRV_M) { > - new_virt =3D (ldn_p(mem_buf, regsz) & BIT(2)) >> 2; > + new_virt =3D (ldn(env, mem_buf, regsz) & BIT(2)) >> 2; > } > > if (riscv_has_ext(env, RVH) && new_virt !=3D env->virt_enabled) = { > -- > 2.53.0 > >