From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gP9cr-0008Fl-Oq for qemu-devel@nongnu.org; Tue, 20 Nov 2018 12:15:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gP9cq-0002w7-M3 for qemu-devel@nongnu.org; Tue, 20 Nov 2018 12:15:49 -0500 Received: from mail-lj1-x244.google.com ([2a00:1450:4864:20::244]:39350) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gP9co-0002p6-Ai for qemu-devel@nongnu.org; Tue, 20 Nov 2018 12:15:48 -0500 Received: by mail-lj1-x244.google.com with SMTP id t9-v6so2322177ljh.6 for ; Tue, 20 Nov 2018 09:15:43 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Alistair Francis Date: Tue, 20 Nov 2018 09:15:15 -0800 Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] hw/arm/stm32f205: Fix the UART and Timer region size List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Peter Maydell , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Seth K , Alistair Francis , "qemu-devel@nongnu.org Developers" , Paolo Bonzini On Mon, Nov 19, 2018 at 3:35 AM Philippe Mathieu-Daud=C3=A9 wrote: > > On Mon, Nov 19, 2018 at 12:08 PM Peter Maydell = wrote: > > On 19 November 2018 at 10:43, Philippe Mathieu-Daud=C3=A9 wrote: > > > Hi Seth, > > > > > > On Mon, Nov 19, 2018 at 4:17 AM Seth K wrote: > > >> > > >> From: Seth Kintigh > > >> > > >> I corrected these 2 memory regions based on specifications from the = chip > > >> manufacturer. The existing ranges seem to overlap and and cause odd > > >> behavior and/or crashes when trying to set up multiple UARTs, > > >> > > >> Signed-off-by: Seth Kintigh > > >> --- > > >> Phil, I hope this is the right format. > > > > > > Better but still incorrect. > > > > What Phil says below is true, but since this is a simple > > patch I have applied it by hand to my target-arm.next branch, > > so it will go into the next release of QEMU. Thanks for your > > contribution! (I rewrote the commit message a bit to make > > it fit in with the usual style we use for our commit messages; > > I hope that's OK.) > > Thanks Peter! > > You can also add: > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Tested-by: Philippe Mathieu-Daud=C3=A9 > > Regards, Thanks for applying this Peter and thanks for the patch Seth. Alistair > > Phil. > > > > > > I tried to apply your patch but get an error: > > > > > > $ git am seth_stm32f2xx_regsize.mbox > > > > I suspect this is because the email is in dual text/HTML format. > > > > thanks > > -- PMM >