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Sun, 10 Jul 2022 23:43:09 -0700 (PDT) MIME-Version: 1.0 References: <20220710082400.29224-1-liweiwei@iscas.ac.cn> <20220710082400.29224-5-liweiwei@iscas.ac.cn> In-Reply-To: <20220710082400.29224-5-liweiwei@iscas.ac.cn> From: Alistair Francis Date: Mon, 11 Jul 2022 16:42:43 +1000 Message-ID: Subject: Re: [PATCH 4/6] target/riscv: add check for csrs existed with U extension To: Weiwei Li Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , wangjunqiang , =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li wrote: > > - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 25 ++++++++++++++++++++++--- > 1 file changed, 22 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 9bda1ff993..0d8e98b7a9 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -339,6 +339,25 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) > > } > > +static RISCVException umode(CPURISCVState *env, int csrno) > +{ > + if (riscv_has_ext(env, RVU)) { > + /* User extension is supported */ > + return RISCV_EXCP_NONE; > + } > + > + return RISCV_EXCP_ILLEGAL_INST; > +} > + > +static RISCVException umode32(CPURISCVState *env, int csrno) > +{ > + if (riscv_cpu_mxl(env) != MXL_RV32) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return umode(env, csrno); > +} > + > /* Checks if PointerMasking registers could be accessed */ > static RISCVException pointer_masking(CPURISCVState *env, int csrno) > { > @@ -3521,7 +3540,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg }, > [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie }, > [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec }, > - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren, > + [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren, > write_mcounteren }, > > [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush }, > @@ -3554,9 +3573,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph }, > > /* Execution environment configuration */ > - [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg, > + [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > - [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, > + [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > -- > 2.17.1 > >