From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>
Cc: Damien Hedde <damien.hedde@greensocs.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine
Date: Tue, 9 Jun 2020 16:09:19 -0700 [thread overview]
Message-ID: <CAKmqyKPe8dBJOmXXS_sUchFPRiExt9Rqn6yUDRM4HT0cm82Nww@mail.gmail.com> (raw)
In-Reply-To: <7bb1bc10-e986-dcbc-630d-99660517c11b@redhat.com>
On Tue, Jun 9, 2020 at 7:21 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote:
>
> On 6/9/20 3:48 PM, Damien Hedde wrote:
> >
> > Hi Alistair,
> >
> > On 5/29/20 12:14 AM, Alistair Francis wrote:
> >> This adds a barebone OpenTitan machine to QEMU.
> >>
> >> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> >> ---
> >
> >> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> >> new file mode 100644
> >> index 0000000000..a4b6499444
> >> --- /dev/null
> >> +++ b/include/hw/riscv/opentitan.h
> >> @@ -0,0 +1,68 @@
> >
> > [...]
> >
> >> +
> >> +static const struct MemmapEntry {
> >> + hwaddr base;
> >> + hwaddr size;
> >> +} ibex_memmap[] = {
> >> + [IBEX_ROM] = { 0x00008000, 0xc000 },
> >
> > Shouldn't the ROM size be 0x4000 (which make the end of rom at 0xc000) ?
> >
> > Not sure if that's exactly this platform you are modeling but the
> > following doc says the ROM size is 16kB (0x4000):
> > https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/doc/_index.md
Yep you are right, I have fixed this.
>
> Good catch. This is why I prefer the IEC notation:
>
> [IBEX_ROM] = { 0x00008000, 16 * KiB },
>
> You can then verify the mapping running 'info mtree' in the monitor.
Thanks!
Alistair
>
> >
> > --
> > Damien
> >
> >
>
next prev parent reply other threads:[~2020-06-09 23:19 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-28 22:14 [PATCH v5 00/11] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-28 22:14 ` [PATCH v5 01/11] riscv/boot: Add a missing header include Alistair Francis
2020-05-28 22:14 ` [PATCH v5 02/11] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-28 22:14 ` [PATCH v5 03/11] target/riscv: Disable the MMU correctly Alistair Francis
2020-06-01 5:24 ` Bin Meng
2020-05-28 22:14 ` [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init Alistair Francis
2020-06-01 5:26 ` Bin Meng
2020-05-28 22:14 ` [PATCH v5 05/11] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-28 22:14 ` [PATCH v5 06/11] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-06-09 13:48 ` Damien Hedde
2020-06-09 14:21 ` Philippe Mathieu-Daudé
2020-06-09 23:09 ` Alistair Francis [this message]
2020-09-08 14:52 ` Peter Maydell
2020-09-09 17:49 ` Alistair Francis
2020-09-09 19:00 ` Peter Maydell
2020-09-09 19:51 ` Palmer Dabbelt
2020-09-10 18:48 ` Alistair Francis
2023-05-19 17:15 ` [PATCH v5 6/11] " Philippe Mathieu-Daudé
2020-05-28 22:14 ` [PATCH v5 07/11] hw/char: Initial commit of Ibex UART Alistair Francis
2020-06-01 21:23 ` Alistair Francis
2020-06-02 11:22 ` LIU Zhiwei
2020-06-02 12:28 ` LIU Zhiwei
2020-06-02 17:54 ` Alistair Francis
2020-06-03 10:33 ` LIU Zhiwei
2020-06-03 15:56 ` Alistair Francis
2020-06-04 1:59 ` LIU Zhiwei
2020-06-04 4:35 ` Alistair Francis
2020-06-04 5:05 ` LIU Zhiwei
2020-06-04 5:46 ` Alistair Francis
2020-06-04 5:40 ` LIU Zhiwei
2020-06-02 17:46 ` Alistair Francis
2020-05-28 22:14 ` [PATCH v5 08/11] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-28 22:14 ` [PATCH v5 09/11] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-28 22:14 ` [PATCH v5 10/11] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-28 22:14 ` [PATCH v5 11/11] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
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