From: Alistair Francis <alistair23@gmail.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com, dbarboza@ventanamicro.com
Subject: Re: [PATCH v2 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
Date: Thu, 15 Feb 2024 13:49:01 +1000 [thread overview]
Message-ID: <CAKmqyKPhZ0WDbdAobUbH34bWoFEW_miSN8yzR2QhFCY1HoJVAQ@mail.gmail.com> (raw)
In-Reply-To: <20240126133101.61344-9-ajones@ventanamicro.com>
On Sat, Jan 27, 2024 at 12:18 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>
> Recent changes in options handling removed the 'mmu' default the bare
> CPUs had, meaning that we must enable 'mmu' by hand when using the
> rva22s64 profile CPU.
>
> Given that this profile is setting a satp mode, it already implies that
> we need a 'mmu'. Enable the 'mmu' in this case.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index da437975b429..88f92d1c7d2c 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -1107,6 +1107,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
>
> #ifndef CONFIG_USER_ONLY
> if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
> + object_property_set_bool(obj, "mmu", true, NULL);
> const char *satp_prop = satp_mode_str(profile->satp_mode,
> riscv_cpu_is_32bit(cpu));
> object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2024-02-15 3:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-26 13:31 [PATCH v2 0/6] riscv: named features riscv,isa, 'svade' rework Andrew Jones
2024-01-26 13:31 ` [PATCH v2 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Andrew Jones
2024-02-15 3:49 ` Alistair Francis [this message]
2024-01-26 13:31 ` [PATCH v2 2/6] target/riscv: add riscv,isa to named features Andrew Jones
2024-02-15 4:06 ` Alistair Francis
2024-01-26 13:31 ` [PATCH v2 3/6] target/riscv: add remaining " Andrew Jones
2024-02-15 4:15 ` Alistair Francis
2024-01-26 13:31 ` [PATCH v2 4/6] target/riscv: Reset henvcfg to zero Andrew Jones
2024-01-26 13:31 ` [PATCH v2 5/6] target/riscv: Gate hardware A/D PTE bit updating Andrew Jones
2024-01-26 13:31 ` [PATCH v2 6/6] target/riscv: Promote svade to a normal extension Andrew Jones
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