[qemu PATCH 0/3] target/riscv: add missing named features

[qemu PATCH 0/3] target/riscv: add missing named features

[Daniel Henrique Barboza]

Hi,

These simple patches add two missing named features in riscv,isa.  Third
patch is a doc change I figured was worth doing.

Drew, as far as Server SoC Reference platform goes, we don't have
'sdext'. I guess we'll have to postpone the Server Soc Ref work for now.

Daniel Henrique Barboza (3):
  target/riscv/cpu.c: add 'sdtrig' in riscv,isa
  target/riscv/cpu.c: add 'ssstrict' to riscv,isa
  target/riscv/cpu.c: do better with 'named features' doc

 target/riscv/cpu.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

-- 
2.49.0

[qemu PATCH 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa

[Daniel Henrique Barboza]

We have support for sdtrig for awhile but we are not advertising it. It
is enabled by default via the 'debug' flag. Use the same flag to also
advertise sdtrig.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fe21e0fb44..9d6fae72b2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -189,6 +189,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
+    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),
     ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
     ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
-- 
2.49.0

[qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa

[Daniel Henrique Barboza]

'ssstrict' is a RVA23 profile-defined extension defined as follows:

"No non-conforming extensions are present. Attempts to execute
unimplemented opcodes or access unimplemented CSRs in the standard or
reserved encoding spaces raises an illegal instruction exception that
results in a contained trap to the supervisor-mode trap handler."

In short, we need to throw an exception when accessing unimplemented
CSRs or opcodes. We do that, so let's advertise it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9d6fae72b2..cd0b159ed5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -217,6 +217,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
     ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm),
     ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
+    ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
     ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
     ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
-- 
2.49.0

[qemu PATCH 3/3] target/riscv/cpu.c: do better with 'named features' doc

[Daniel Henrique Barboza]

Most of the named features are added directly in isa_edata_arr[], some
of them are also added in riscv_cpu_named_features(). There is a reason
for that, and the existing docs can do better explaining it.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cd0b159ed5..fdf2eb2b1c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1377,13 +1377,23 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
  * 'Named features' is the name we give to extensions that we
  * don't want to expose to users. They are either immutable
  * (always enabled/disable) or they'll vary depending on
- * the resulting CPU state. They have riscv,isa strings
- * and priv_ver like regular extensions.
+ * the resulting CPU state.
+ *
+ * Some of them are always enabled depending on priv version
+ * of the CPU and are declared directly in isa_edata_arr[].
+ * The ones listed here have special checks during finalize()
+ * time and require their own flags like regular extensions.
+ * See riscv_cpu_update_named_features() for more info.
  */
 const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
     MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
     MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
     MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
+
+    /*
+     * 'ziccrse' has its own flag because the KVM driver
+     * wants to enable/disable it on its own accord.
+     */
     MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
 
     { },
-- 
2.49.0

Re: [qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa

[Andrew Jones]

On Thu, May 29, 2025 at 05:23:14PM -0300, Daniel Henrique Barboza wrote:
> 'ssstrict' is a RVA23 profile-defined extension defined as follows:
> 
> "No non-conforming extensions are present. Attempts to execute
> unimplemented opcodes or access unimplemented CSRs in the standard or
> reserved encoding spaces raises an illegal instruction exception that
> results in a contained trap to the supervisor-mode trap handler."
> 
> In short, we need to throw an exception when accessing unimplemented
> CSRs or opcodes. We do that, so let's advertise it.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9d6fae72b2..cd0b159ed5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -217,6 +217,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
>      ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm),
>      ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
> +    ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
>      ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> -- 
> 2.49.0
> 
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Re: [qemu PATCH 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa

[Alistair Francis]

On Fri, May 30, 2025 at 6:24 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> We have support for sdtrig for awhile but we are not advertising it. It
> is enabled by default via the 'debug' flag. Use the same flag to also
> advertise sdtrig.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fe21e0fb44..9d6fae72b2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -189,6 +189,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
>      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
>      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> +    ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),
>      ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
>      ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
> --
> 2.49.0
>
>

Re: [qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa

[Alistair Francis]

On Fri, May 30, 2025 at 6:24 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> 'ssstrict' is a RVA23 profile-defined extension defined as follows:
>
> "No non-conforming extensions are present. Attempts to execute
> unimplemented opcodes or access unimplemented CSRs in the standard or
> reserved encoding spaces raises an illegal instruction exception that
> results in a contained trap to the supervisor-mode trap handler."
>
> In short, we need to throw an exception when accessing unimplemented
> CSRs or opcodes. We do that, so let's advertise it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9d6fae72b2..cd0b159ed5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -217,6 +217,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
>      ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm),
>      ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
> +    ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
>      ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
>      ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> --
> 2.49.0
>
>

Re: [qemu PATCH 3/3] target/riscv/cpu.c: do better with 'named features' doc

[Alistair Francis]

On Fri, May 30, 2025 at 6:24 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Most of the named features are added directly in isa_edata_arr[], some
> of them are also added in riscv_cpu_named_features(). There is a reason
> for that, and the existing docs can do better explaining it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cd0b159ed5..fdf2eb2b1c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1377,13 +1377,23 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
>   * 'Named features' is the name we give to extensions that we
>   * don't want to expose to users. They are either immutable
>   * (always enabled/disable) or they'll vary depending on
> - * the resulting CPU state. They have riscv,isa strings
> - * and priv_ver like regular extensions.
> + * the resulting CPU state.
> + *
> + * Some of them are always enabled depending on priv version
> + * of the CPU and are declared directly in isa_edata_arr[].
> + * The ones listed here have special checks during finalize()
> + * time and require their own flags like regular extensions.
> + * See riscv_cpu_update_named_features() for more info.
>   */
>  const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
>      MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>      MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
>      MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
> +
> +    /*
> +     * 'ziccrse' has its own flag because the KVM driver
> +     * wants to enable/disable it on its own accord.
> +     */
>      MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
>
>      { },
> --
> 2.49.0
>
>

Re: [qemu PATCH 0/3] target/riscv: add missing named features

[Alistair Francis]

On Fri, May 30, 2025 at 6:24 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> These simple patches add two missing named features in riscv,isa.  Third
> patch is a doc change I figured was worth doing.
>
> Drew, as far as Server SoC Reference platform goes, we don't have
> 'sdext'. I guess we'll have to postpone the Server Soc Ref work for now.
>
> Daniel Henrique Barboza (3):
>   target/riscv/cpu.c: add 'sdtrig' in riscv,isa
>   target/riscv/cpu.c: add 'ssstrict' to riscv,isa
>   target/riscv/cpu.c: do better with 'named features' doc

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>
> --
> 2.49.0
>
>

Re: [qemu PATCH 0/3] target/riscv: add missing named features

[Daniel Henrique Barboza]

Alistair,


This series is breaking bios-table-test on patches 1 and 2 because we're
adding more stuff in the default riscv,isa and I forgot to update the
bios table.

I'll send a v2. Thanks,


Daniel

On 5/29/25 5:23 PM, Daniel Henrique Barboza wrote:
> Hi,
> 
> These simple patches add two missing named features in riscv,isa.  Third
> patch is a doc change I figured was worth doing.
> 
> Drew, as far as Server SoC Reference platform goes, we don't have
> 'sdext'. I guess we'll have to postpone the Server Soc Ref work for now.
> 
> Daniel Henrique Barboza (3):
>    target/riscv/cpu.c: add 'sdtrig' in riscv,isa
>    target/riscv/cpu.c: add 'ssstrict' to riscv,isa
>    target/riscv/cpu.c: do better with 'named features' doc
> 
>   target/riscv/cpu.c | 16 ++++++++++++++--
>   1 file changed, 14 insertions(+), 2 deletions(-)
>