From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
richard.henderson@linaro.org
Subject: Re: [PATCH v3 1/3] target/riscv: Remove redundant insn length check for zama16b
Date: Mon, 5 Aug 2024 09:52:51 +1000 [thread overview]
Message-ID: <CAKmqyKPoHZmwu-=A8wfKM6V=k3Zb2__6erTFULm_A6fg2n7dhw@mail.gmail.com> (raw)
In-Reply-To: <20240802072417.659-2-zhiwei_liu@linux.alibaba.com>
On Fri, Aug 2, 2024 at 5:26 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> Compressed encodings also applies to zama16b.
> https://github.com/riscv/riscv-isa-manual/pull/1557
>
> Suggested-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--
> target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
> 3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
> index 1f5fac65a2..0ac42c3223 100644
> --- a/target/riscv/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
> @@ -47,7 +47,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> + if (ctx->cfg_ptr->ext_zama16b) {
> memop |= MO_ATOM_WITHIN16;
> }
>
> @@ -67,7 +67,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVD);
>
> - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> + if (ctx->cfg_ptr->ext_zama16b) {
> memop |= MO_ATOM_WITHIN16;
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
> index f771aa1939..0222a728df 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVF);
>
> - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> + if (ctx->cfg_ptr->ext_zama16b) {
> memop |= MO_ATOM_WITHIN16;
> }
>
> @@ -70,7 +70,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
> REQUIRE_FPU;
> REQUIRE_EXT(ctx, RVF);
>
> - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> + if (ctx->cfg_ptr->ext_zama16b) {
> memop |= MO_ATOM_WITHIN16;
> }
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
> index 98e3806d5e..fab5c06719 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -268,7 +268,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
> {
> bool out;
>
> - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> + if (ctx->cfg_ptr->ext_zama16b) {
> memop |= MO_ATOM_WITHIN16;
> }
> decode_save_opc(ctx);
> @@ -369,7 +369,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
>
> static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
> {
> - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
> + if (ctx->cfg_ptr->ext_zama16b) {
> memop |= MO_ATOM_WITHIN16;
> }
> decode_save_opc(ctx);
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2024-08-04 23:54 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-02 7:24 [PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b LIU Zhiwei
2024-08-02 7:24 ` [PATCH v3 1/3] " LIU Zhiwei
2024-08-02 7:53 ` Richard Henderson
2024-08-04 23:52 ` Alistair Francis [this message]
2024-08-02 7:24 ` [PATCH v3 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b LIU Zhiwei
2024-08-02 7:54 ` Richard Henderson
2024-08-04 23:54 ` Alistair Francis
2024-08-02 7:24 ` [PATCH v3 3/3] target/riscv: Relax fld alignment requirement LIU Zhiwei
2024-08-02 7:54 ` Richard Henderson
2024-08-04 23:56 ` Alistair Francis
2024-08-05 1:51 ` [PATCH v3 0/3] target/riscv: Remove redundant insn length check for zama16b Alistair Francis
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