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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a31; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Aug 2, 2024 at 5:26=E2=80=AFPM LIU Zhiwei wrote: > > Compressed encodings also applies to zama16b. > https://github.com/riscv/riscv-isa-manual/pull/1557 > > Suggested-by: Alistair Francis > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- > target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- > target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- > 3 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_= trans/trans_rvd.c.inc > index 1f5fac65a2..0ac42c3223 100644 > --- a/target/riscv/insn_trans/trans_rvd.c.inc > +++ b/target/riscv/insn_trans/trans_rvd.c.inc > @@ -47,7 +47,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); > > - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { > + if (ctx->cfg_ptr->ext_zama16b) { > memop |=3D MO_ATOM_WITHIN16; > } > > @@ -67,7 +67,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); > > - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { > + if (ctx->cfg_ptr->ext_zama16b) { > memop |=3D MO_ATOM_WITHIN16; > } > > diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_= trans/trans_rvf.c.inc > index f771aa1939..0222a728df 100644 > --- a/target/riscv/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > @@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVF); > > - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { > + if (ctx->cfg_ptr->ext_zama16b) { > memop |=3D MO_ATOM_WITHIN16; > } > > @@ -70,7 +70,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVF); > > - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { > + if (ctx->cfg_ptr->ext_zama16b) { > memop |=3D MO_ATOM_WITHIN16; > } > > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_= trans/trans_rvi.c.inc > index 98e3806d5e..fab5c06719 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -268,7 +268,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, Me= mOp memop) > { > bool out; > > - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { > + if (ctx->cfg_ptr->ext_zama16b) { > memop |=3D MO_ATOM_WITHIN16; > } > decode_save_opc(ctx); > @@ -369,7 +369,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb = *a, MemOp memop) > > static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) > { > - if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len !=3D 2)) { > + if (ctx->cfg_ptr->ext_zama16b) { > memop |=3D MO_ATOM_WITHIN16; > } > decode_save_opc(ctx); > -- > 2.25.1 > >